Dual lead frame semiconductor package and method of manufacture

Patent metadata

Field	Value
Publication number	US-9595503-B2
Application number	US-201414474420-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Sep 9, 2010
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

First claim

What is claimed is:

1. A method for making a semiconductor package, comprising:
disposing at least one IC chip on a substrate frame, wherein
the substrate lead frame includes at least one first substrate lead coupled to a substrate frame, at least one second substrate lead and at least one third substrate lead facing a side of the first substrate, at least one first extension portion each coupling as respective at least one second substrate lead to the substrate frame, and at least one second extension portion each coupling a respective at least one third substrate lead to the substrate frame,
each of the at least one IC chip has a lower surface including a first conductive region and an upper surface including a second conductive region and a third conductive region, and
the first conductive region of each at least one IC chip is aligned with a respective first substrate lead on the substrate lead frame;

disposing a clip lead frame on the at least one IC chip and the substrate frame, wherein
the clip lead frame includes at least one first clip lead coupled to a clip frame and at least one second clip lead coupled to the clip frame, and
each of the at least one first clip lead of the clip lead frame is aligned between a respective second conductive region of each of the at least one IC chip and a respective at least one second substrate lead, and
each at least one second clip lead is aligned between a respective third conductive region of each of the at least one IC chip and as respective at least one third substrate lead;

electrically and mechanically coupling the substrate lead frame, the at least one IC chip and the clip lead frame together, wherein
the first conductive region of each at least one IC chip is electrically coupled to the respective first substrate lead on the substrate lead frame,
each of the at least one first clip lead of the clip lead frame is electrically coupled between a respective second conductive region of each of the at least one IC chip and a respective at least one second substrate lead, and
each of the at least one second clip lead is electrically coupled between a respective third conductive region of each of the at least one IC chip and a respective at least one third substrate lead,

encapsulating the substrate lead frame, the at least one IC chip and the clip lead frame electrically and mechanically coupled together in a molding compound, wherein each of the at least one first substrate lead, the at least one second substrate lead and the at least one third substrate lead are exposed outside the molding compound; and
cutting the substrate lead frame, the at least one IC chip and the clip lead frame electrically and mechanically coupled together in the molding compound to form at least one semiconductor package each including at least one IC chip, wherein the first clip lead remains electrically coupled between the second conductive region of the at least one IC chip and the at least one second substrate lead, and the second clip lead remains electrically coupled between the third conductive region of the at least one IC chip and the at least on third substrate lead.

2. The method according to claim 1 , wherein the substrate lead frame further comprises a plurality of fixed connection segments, for connecting the substrate frame, the at least one first substrate lead, the at least one second substrate lead, and the at least one third substrate lead.

3. The method according, to claim 1 , wherein a space exists between the second substrate lead and the side of the first substrate lead and between the third substrate lead and the side of the first substrate lead.

4. The method according to claim 1 , wherein electrically and mechanically coupling the substrate lead frame, the at least one IC chip and the clip lead frame together comprises:
forming a first solder on the first substrate lead, the second substrate lead, and the third substrate lead;
forming a second solder on the first clip lead and the second clip lead; and
performing a solder reflow process.

5. The method according to claim 1 , wherein the at least one first clip lead has a first end and a second end, the at least one second clip lead has a third end and a fourth end, and both the second end of the at least one first clip lead and the fourth end of the at least one second clip lead are coupled to at least one intermediate connection segment; and the first end of the first clip lead is electrically connected to the second conductive region of the at least one chip, and the third end of the second clip lead is electrically connected to the third conductive region of the at least one chip.

6. The method according to claim 1 , wherein the at least one first clip lead has a first recess and a second recess, the at least one second clip lead has a third recess and a fourth recess, the at least one first clip lead is electrically connected to the second conductive region of the at least one chip through the first recess, the at least one first clip lead is electrically connected to the second substrate lead through the second recess, the second clip lead is electrically connected to the third conductive region of the at least one chip through the third recess, and the second clip lead is electrically connected to the third substrate lead through the fourth recess.

7. The method according to claim 1 , wherein the first substrate lead is a drain pin, the second substrate lead is a source pin, the third substrate lead is a gate pin, the first conductive region is a drain conductive region, the second conductive region is a source conductive region, the third conductive region is a gate conductive region, the first clip lead is a source connection segment, and the second clip lead is a gate connection segment.

8. The method according to claim 1 , wherein the first substrate lead is a source pin, the second substrate lead is a drain pin, the third substrate lead is a gate pin, the first conductive region is a source conductive region, the second conductive region is a drain conductive region, the third conductive region is a gate conductive region, the first clip lead is a drain connection segment, and the second clip lead is a gate connection segment.

Assignees

• Kuo Frank
• Belani Suresh
• Vishay Siliconix

Inventors

• Kuo Frank
• Belani Suresh

Classifications

• H10W72/07652

  changes in structures or sizes · CPC title

• H10W72/627

  Multiple strap connectors having different structures or shapes · CPC title

• H10W72/07653

  changes in shapes · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title