Semiconductor device including an epitaxy region

Patent metadata

Field	Value
Publication number	US-9595477-B2
Application number	US-201113010028-A
Country	US
Kind code	B2
Filing date	Jan 20, 2011
Priority date	Jan 20, 2011
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

First claim

What is claimed is:

1. A method comprising:
forming a gate structure over a substrate;
forming lightly doped source and drain (LDD) regions in the substrate, wherein the gate structure is disposed between the LDD regions;
after forming the LDD regions, forming a conformal first spacer material layer by depositing SiCN abutting a top surface and sidewalls of the gate structure on the substrate;
forming a conformal second spacer material layer overlying the first spacer material layer, wherein the conformal second spacer material layer overlies the top surface and sidewalls of the gate structure;
etching the conformal first spacer material layer and the conformal second spacer material layer concurrently to form a first spacer and a second spacer respectively, wherein the etching includes removing the first spacer material layer and the second spacer material layer from the top surface of the gate structure;
forming an epitaxy region on the substrate over the LDD regions, wherein the epitaxy region interfaces the first and second spacers;
after forming the epitaxy region, removing the second spacer to provide a space, wherein the space has a width defined by a first vertical sidewall of the epitaxy region and a vertical sidewall of the first spacer, the distance there between providing the width of the space;
using one deposition process, forming an interlayer dielectric layer (ILD) in the space; and
forming a contact feature in the ILD layer and contacting the epitaxy region.

2. The method of claim 1 , wherein the epitaxy region forms a raised source/drain region.

3. The method of claim 1 , wherein the ILD layer includes an interface with the first spacer.

4. The method of claim 1 , wherein the forming the second spacer material layer includes depositing silicon nitride.

5. The method of claim 1 , wherein the etching the first spacer material layer and the second spacer material layer concurrently includes removing the first spacer material layer from a top surface of the gate structure and exposing a region of the substrate wherein the epitaxy region will be formed.

6. The method of claim 1 , wherein the gate structure includes polysilicon.

7. The method of claim 6 , wherein the gate structure includes a hard mask layer overlying the polysilicon.

8. The method of claim 1 , wherein the forming the first spacer material layer includes forming a conformal layer, which is not etched prior to forming the second spacer material layer.

9. The method of claim 1 , further comprising:
removing the gate structure from the substrate, wherein the removing the gate structure provides a trench having sidewalls defined by the first spacer material.

10. The method of claim 1 , where the forming the contact feature in the ILD includes forming the contact feature in the ILD such that two opposing sidewalls of the contact feature interface the ILD.

11. The method of claim 1 , wherein the forming the interlayer dielectric layer (ILD) in the space includes providing an interface between the ILD and the vertical sidewall of the first spacer, a lateral surface of the first spacer, the first vertical sidewall of the epitaxy region and a sidewall of the contact feature.

12. A method comprising:
forming a gate structure over a substrate;
forming lightly doped source and drain (LDD) regions in the substrate, wherein the gate structure is disposed between the LDD regions;
after forming the LDD regions, forming a first spacer material layer abutting the gate structure, wherein the first spacer material is SiCN;
forming a second spacer material layer overlying the first spacer material layer;
etching the first spacer material layer and the second spacer material layer to form a first and a second spacer respectively;
forming an epitaxy feature over the LDD regions in the substrate, wherein the epitaxy feature physically interfaces with the first and second spacers;
removing the second spacer after forming the epitaxy feature;
using a single deposition process, forming a dielectric layer including in a region between a vertical sidewall of the epitaxy feature and a vertical sidewall of the first spacer and also on the epitaxy feature; and
forming a contact feature in the dielectric layer and on the epitaxy feature after removing the second spacer.

13. The method of claim 12 , wherein the forming the epitaxy feature includes forming a raised source/drain of a transistor associated with the gate structure.

Assignees

• Pan Te-Jen
• Lin Yu-Hsien
• Shen Hsiang-Ku
• Fan Wei-Han
• Lin Yun Jing
• Huang Yimin
• Wang Tzu-Chung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pan Te-Jen
• Lin Yu-Hsien
• Shen Hsiang-Ku
• Fan Wei-Han
• Lin Yun Jing
• Huang Yimin
• Wang Tzu-Chung

Classifications

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H01L21/823864

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L21/823828

  Electricity · mapped topic