Nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9595331-B1
Application number	US-201615019450-A
Country	US
Kind code	B1
Filing date	Feb 9, 2016
Priority date	Oct 26, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A nonvolatile memory device may include a plurality of memory blocks each including a drain select line, word lines and a source select line, and a pass transistor stage including a plurality of pass transistors formed in series in an active region and suitable for transferring word line voltages to a memory block selected among the memory blocks, in response to a block select signal, wherein the pass transistors each share a drain with a first adjacent pass transistor at one side while sharing a source with a second adjacent pass transistor at the other, and wherein a pair of pass transistors which share the source transfer word line driving signal form drains thereof to a pair of word lines which are included in different memory blocks among the memory blocks, through the source.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a plurality of memory blocks each memory block including a drain select line, word lines and a source select line; and
a pass transistor stage including a plurality of pass transistors for transferring word line voltages to a memory block selected in response to a block select signal, wherein the pass transistors are connected in series and formed in an active region such that each pass transistor shares a drain with a first adjacent pass transistor at one side and shares a source with a second adjacent pass transistor at another side;
wherein a pair of pass transistors which share the source transfer word line driving signals from drains thereof to a pair of word lines included in a different memory block from the one containing the pair of pass transistors.

2. The nonvolatile memory device according to claim 1 , wherein, in a pair of pass transistors which share the drain or the source, different block select signals are inputted to a gate of one pass transistor and a gate of the other pass transistor.

3. The nonvolatile memory device according to claim 1 , wherein the active region has a line shape extending in the same direction as an arrangement direction of the memory blocks.

4. The nonvolatile memory device according to claim 1 , further comprising:
driving signal lines suitable for electrically coupling sources of the pass transistors and word lines of the memory blocks.

5. The nonvolatile memory device according to claim 4 , wherein the driving signal lines comprise:
first signal lines suitable for transferring the word line driving signals in a direction parallel to the direction in which the active region extends; and
second signal lines suitable for transferring the word line driving signals in a direction perpendicular to the direction in which the active region extends.

6. The nonvolatile memory device according to claim 5 , wherein the first signal lines are disposed over the active region.

7. The nonvolatile memory device according to claim 5 , wherein each of the memory blocks include a slimming region where edge portions of the drain select line, the word lines and the source select line are exposed in the form of a stair, and the first signal lines are disposed over the slimming region.

8. The nonvolatile memory device according to claim 5 , wherein the first signal lines and the second signal lines are disposed in different metal layers.

9. The nonvolatile memory device according to claim 8 , further comprising:
global word lines disposed in a direction parallel to the direction in which the active region extends, and suitable for transferring the word line driving signals,
wherein the first signal lines are disposed in the same metal layer as the global word lines.

10. The nonvolatile memory device according to claim 5 , wherein the pass transistors comprise:
first pass transistors, each disposed at an end of the active region, and suitable for sharing a drain with an adjacent pass transistor without sharing a source; and
second pass transistors each disposed at an inner part of the active region, and suitable for sharing a drain and a source with adjacent pass transistors.

11. The nonvolatile memory device according to claim 10 , wherein each of the first transistors transfer a word line driving signal from the drain thereof to one of word lines of a memory block through the source thereof.

12. The nonvolatile memory device according to claim 10 , further comprising:
one or more third pass transistors each including a source and a drain formed in an additional active region defined separately from the active region,
wherein the third pass transistor transfers a word line driving signal from the drain thereof to one of word lines of a memory block, among the memory blocks, through the source thereof.

13. The nonvolatile memory device according to claim 10 , wherein the active region is formed in a plural, the first pass transistors are paired to be electrically coupled in common to one of the first signal lines, and each pair of the first pass transistors are driven by different block select signals.

14. The nonvolatile memory device according to claim 12 , wherein the word lines of each of the memory blocks comprise:
a plurality of main word lines; and
one or more dummy word lines disposed between the drain select line and the main word lines.

15. The nonvolatile memory device according to claim 14 ,
wherein, among the word lines, an outermost main word line adjoining the drain select line, an adjacent main word line adjoining the outermost main word line, and the dummy word line are each electrically coupled to one of the first pass transistors and the third pass transistor, and provided with a word line driving signal from the one of the first pass transistors and the third pass transistor, and
wherein, among the word lines, remaining word lines excluding the outermost main word line, the adjacent main word line, and the dummy word line are each electrically coupled to a pair of second pass transistors which share a source, and provided with a word line driving signal from the pair of second pass transistors which share the source.

16. The nonvolatile memory device according to claim 14 , wherein each of the main word lines and the dummy word line of each of the memory blocks is electrically coupled to a pair of second pass transistors sharing a source, and is provided with a word line driving signal from the pair of second pass transistors sharing the source.

17. The nonvolatile memory device according to claim 16 , wherein, among the memory blocks, an outermost main word line, an adjacent main word line, and a dummy word line of a first memory blocks are paired with remaining word lines of a second memory block excluding an outermost main word line, an adjacent main word line, and a dummy word line of a second memory block, and each pair of word lines are provided with the same word line driving signal from the pass transistor stage.

18. The nonvolatile memory device according to claim 17 , wherein, in the case where a remaining word line of the second memory block which is paired with the outermost main word line of the first memory block is selected and a program voltage is provided as a word line driving signal to the unselected outermost main word line of the first memory block, a higher pass voltage is provided as a word line driving signal to the adjacent main word line and the dummy word line of the first memory block than remaining word lines of the first memory block.

19. The nonvolatile memory device according to claim 17 , wherein, in the case where a remaining word line of the second memory block which is paired with the outermost main word line of the first memory block is selected and a program voltage is provided as a word line driving signal to the unselected outermost main word line of the first memory block, a decoupling voltage is provided as a word line driving signal to the adjacent main word line and the dummy word line of the first memory block.

20. The nonvolatile memory device according to claim 19 , wherein the decoupling voltage is 0V.

Assignees

• Sk Hynix Inc

Inventors

• Lee Go-Hyun
• Kim Jin Ho
• Baek Ji Hui
• Jung Sung Wook

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title