Semiconductor memory device and method for operating the same

Patent metadata

Field	Value
Publication number	US-9595309-B2
Application number	US-201614997775-A
Country	US
Kind code	B2
Filing date	Jan 18, 2016
Priority date	Jul 22, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A semiconductor memory device includes a plurality of memory cells coupled to multiple word lines a word line deactivation voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to temperature ranges, and a word line driving block suitable for driving a word line to be deactivated with the word line deactivation voltages selected from the word line deactivation voltages.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of memory cells coupled to multiple word lines;
an off voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to a plurality of temperatures;
a word line driving block suitable for driving a word line to be deactivated with a word line deactivation voltage selected from the word line deactivation voltages; and
a temperature detection block suitable for generating a plurality of detection signals corresponding to the plurality of temperatures and supplying the detection signals to the off voltage generation block,
wherein the off voltage generation block includes:
a plurality of voltage generation units suitable for generating a plurality of internal voltages; and
a multiplexing unit suitable for outputting one of the internal voltages as the word line deactivation voltage in response to the detection signal.

2. The semiconductor memory device of claim 1 , wherein the word line deactivation voltages correspond to the plurality of the detection signals.

3. The semiconductor memory device of claim 1 , further comprising:
an active voltage generation block suitable for generating an active voltage for activating a word line and supplying the active voltage to the word line driving block.

4. The semiconductor memory device of claim 1 , wherein the voltage level of the word line deactivation voltage gets lower as a temperature gets higher.

5. The semiconductor memory device of claim 1 , wherein the word line driving block includes:
a driving unit suitable for driving a selected word line; and
a voltage set unit suitable for supplying the word line deactivation voltage or a predetermined voltage to the driving unit in response to state information of a memory cell coupled to the corresponding word line.

6. A semiconductor memory device, comprising:
a plurality of memory cells coupled to multiple word lines;
a plurality of temperature detection blocks corresponding to temperature ranges that are set based on state information of the memory cells;
a plurality of off voltage generation blocks suitable for generating word line deactivation voltages having different voltage levels corresponding to output signals of the temperature detection blocks; and
a plurality of word line driving blocks suitable for driving a word line to be deactivated with the word line deactivation voltage selected from the word line deactivation voltages,
wherein the word line deactivation voltage has a first voltage level when a operation state or a process state of the memory cells is good, and the word line deactivation voltage has a second voltage level which is lower than the first voltage level when the operation state or the process state of the memory cells is bad.

7. The semiconductor memory device of claim 6 , further comprising:
an active voltage generation block suitable for generating an active voltage for activating the word lines and supplying the active voltage to the word line driving blocks.

8. The semiconductor memory device of claim 6 , wherein the voltage level of the word line deactivation voltage gets lower as a temperature gets higher.

9. The semiconductor memory device of claim 6 , wherein some of the word lines have the word line deactivation voltage having the first voltage level, and the other word lines have the word line deactivation voltage having the second voltage level.

10. A semiconductor memory device, comprising:
a plurality of memory cells coupled to multiple word lines;
an off voltage generation block suitable for generating word line deactivation voltages having different voltage levels corresponding to a plurality of temperatures;
a word line driving block suitable for driving a word line to be deactivated with a word line deactivation voltage selected from the word line deactivation voltages; and
a temperature detection block suitable for generating a plurality of detection signals corresponding to the plurality of temperatures and supplying the detection signals to the off voltage generation block,
wherein the off voltage generation block further includes:
a voltage generation unit suitable for generating the word line deactivation voltages; and
a trimming unit suitable for controlling the word line deactivation voltages to the predetermined voltage during a training operation.

11. The semiconductor memory device of claim 10 , further comprising:
a training control block suitable for controlling the trimming unit during the training operation, and controlling the trimming unit in response to the detection signal during a normal operation.

12. The semiconductor memory device of claim 11 , wherein the training control block includes:
a first control signal generation unit suitable for generating a control signal for controlling the voltage level of the word line deactivation voltage during the training operation;
a second control signal generation unit suitable for generating a control signal for controlling the voltage level of the word line deactivation voltage to have a voltage level corresponding to the detection signal during the normal operation; and
a multiplexing unit suitable for outputting one of the first and second control signal generation units through the training operation and the normal operation.

13. The semiconductor memory device of claim 12 , wherein the second control signal generation unit receives information corresponding to the control signal of the first control signal generation unit after the training operation is completed.

14. The semiconductor memory device of claim 10 , wherein the word line driving block includes:
a driving unit suitable for driving a selected word line; and
a voltage set unit suitable for supplying the word line deactivation voltage or a predetermined voltage to the driving unit in response to state information of a memory cell coupled to the corresponding word line.

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang-Hyun
• Kim Min-Chang
• Lee Do-Yun
• Lee Jae-Jin
• Jung Hun-Sam

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/10

  Decoders · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C8/00

  Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) · CPC title