Architecture and method for managing interrupts in a virtualized environment

Patent metadata

Field	Value
Publication number	US-9594703-B2
Application number	US-201213976999-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Mar 29, 2012
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system. Other embodiments are disclosed and claimed.

First claim

The invention claimed is:

1. A computer implemented method, comprising:
identifying a signal indicating real-time mode operation for a guest operating system (OS);
disabling halt (HLT) exiting for the guest OS;
directly routing an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system;
programming a virtual advanced programmable interrupt controller (APIC) coupled to the first processor to prevent a virtual machine (VM) exit when an end-of-interrupt (EOI) is generated; and
forwarding the EOI to a virtualized APIC page for processing.

2. The computer implemented method of claim 1 , comprising, in response to the signal, clearing a bit in a virtual machine control structure (VMCS) that indicates an external interrupt is to generate the VM exit wherein a transition from execution by the guest OS to execution by a host system occurs.

3. The computer implemented method of claim 1 , comprising pinning the guest OS to the first processor during real-time operation of the guest OS.

4. The computer implemented method of claim 1 , comprising disabling HLT exiting for the guest OS by setting a value of a bit indicating whether the VM exit is to be performed when the guest OS executes an HLT instruction.

5. The computer implemented method of claim 1 , comprising instructing a bootstrap processor to forward an interrupt generated by a hard drive as an inter-processor-interrupt (IPI) to the guest OS.

6. The computer implemented method of claim 1 , comprising setting a direct translation structure for interrupts to be forwarded to the guest OS.

7. The computer implemented method of claim 1 , comprising translating the interrupts into an interrupt format of the guest operating system.

8. An apparatus, comprising:
a processor circuit;
a real-time interrupt module operable on the processor circuit to:
identify a signal received from a guest operating system (OS) running on a first processor, the signal indicating real-time mode operation for the guest OS;
disable halt (HLT) exiting for the guest OS;
directly route an interrupt for the first processor to the guest OS without causing a transition from a non-root mode of operation to a root mode of operation;
program a virtual advanced programmable interrupt controller (APIC) coupled to the first processor to prevent a virtual machine (VM) exit when an end-of-interrupt (EOI) is generated; and
forward the EOI to a virtualized APIC page for processing.

9. The apparatus of claim 8 , the real-time interrupt module operable on the processor circuit to a clear a bit in a virtual machine control structure (VMCS) that indicates an external interrupt is to generate the VM exit in response to the signal.

10. The apparatus of claim 8 , the real-time interrupt module operable on the processor circuit to pin the guest OS to the first processor during real-time operation of the guest OS.

11. The apparatus of claim 8 , the real-time interrupt module operable on the processor circuit to disable HLT exiting for the guest OS by setting a value of a bit indicating whether the VM exit is to be performed when the guest OS executes an HLT instruction.

12. The apparatus of claim 8 , the real-time interrupt module operable on the processor circuit to translate the interrupts into an interrupt format of the guest OS during real-time operation of the guest OS.

13. The apparatus of claim 8 , the real-time interrupt module operable on the processor circuit to direct the bootstrap processor to output an external interrupt as an inter-processor interrupt for forwarding to the guest OS.

14. The apparatus of claim 8 , comprising a digital display to present output of the guest OS.

15. At least one machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to:
identify a signal indicating real-time mode operation for a guest operating system (OS);
disable halt (HLT) exiting for the guest OS;
directly route an interrupt for a first processor to the guest OS while the guest OS is running without causing a transition from execution by the guest OS to execution by a host system;
program a virtual advanced programmable interrupt controller (APIC) coupled to the first processor to prevent a virtual machine (VM) exit when an end-of-interrupt (EOI) is generated; and
forward the EOI to a virtualized APIC page for processing.

16. The at least one machine readable medium of claim 15 , the computing device caused to in response to the signal, clear a bit in a virtual machine control structure (VMCS) that indicates an external interrupt is to generate the VM exit wherein a transition from execution by the guest OS to execution by a host system occurs.

17. The at least one machine readable medium of claim 15 , the computing device caused to pin the guest OS to the first processor during real-time operation of the guest OS.

18. The at least one machine readable medium of claim 15 , the computing device caused to disable HLT exiting for the guest OS by setting a value of a bit indicating whether the VM exit is to be performed when the guest OS executes an HLT instruction.

19. The at least one machine readable medium of claim 15 , the computing device caused to instruct a bootstrap processor to forward an interrupt generated by a hard drive as an inter-processor-interrupt (IPI) to the guest OS.

20. The at least one machine readable medium of claim 15 , the computing device caused to set a direct translation structure for interrupts to be forwarded to the guest OS.

21. The at least one machine readable medium of claim 15 , the computing device caused to translate the interrupts into an interrupt format of the guest operating system.

Assignees

• Coleman James A
• Oehrlein Scott M
• Intel Corp

Inventors

• Coleman James A
• Oehrlein Scott M

Classifications

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title