Criteria for selection of data for a secondary cache

Patent metadata

Field	Value
Publication number	US-9594685-B2
Application number	US-201213542990-A
Country	US
Kind code	B2
Filing date	Jul 6, 2012
Priority date	Jul 6, 2012
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Host read operations affecting a first logical block address of a data storage device are tracked. The data storage device includes a main storage and a non-volatile cache that mirrors a portion of data of the main storage. One or more criteria associated with the host read operations are determined. The criteria are indicative of future read requests of second logical block address associated with the first logical block address. Data of the at least the second logical block address is copied from the main storage to the non-volatile cache if the criteria meets a threshold.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor configured to:
track host read operations affecting a first logical block address of a data storage device, the data storage device comprising a main storage and a non-volatile cache that stores read-only data and mirrors a portion of data of the main storage;
determine criteria associated with the host read operations, the criteria being indicative of future read requests of a second logical block address associated with the first logical block address and wherein an importance of the criteria is reduced based on write activity associated with the first logical block address; and
cause data of at least the second logical block address from the main storage to be copied to the non-volatile cache if the criteria meets a threshold.

2. The apparatus of claim 1 , wherein the criteria is indicative of a recent proximity in time of the host read operations.

3. The apparatus of claim 1 , wherein the criteria is indicative of a closeness of address values of the host read operations.

4. The apparatus of claim 1 , wherein the importance of the criteria is increased based on a predicted main store access penalty resulting from a secondary cache miss in response to a request for the second logical block address.

5. The apparatus of claim 1 , wherein the processor is further configured to maintain a plurality of data structures each associated with a logical block address range, wherein each of the data structures stores indicators indicative of the recent operations affecting the associated logical block address range, the indicators used to determine the criteria associated with the first logical block address.

6. The apparatus of claim 1 , wherein the processor is further configured to maintain a plurality of data structures each associated with a time range, wherein each of the data structures stores indicators indicative of spatial locality of a logical block address range, the indicators used to determine the criteria associated with the first logical block address.

7. The apparatus of claim 1 , wherein the main storage comprises a magnetic disk media and the non-volatile cache comprises a non-volatile, solid-state memory.

8. A method, comprising:
tracking host read operations affecting a first logical block address of a data storage device, the data storage device comprising a main storage and a non-volatile cache that stores read-only data and mirrors a portion of data of the main storage;
determining criteria associated with the host read operations, the criteria being indicative of future read requests of a second logical block address associated with the first logical block address and wherein an importance of the criteria is reduced based on write activity associated with the first logical block address; and
causing data of at least the second logical block address from the main storage to be copied to the non-volatile cache if the criteria meets a threshold.

9. The method of claim 8 , wherein the criteria is indicative of a recent proximity in time of the host read operations.

10. The method of claim 8 , wherein the criteria is indicative of a closeness of address values of the host read operations.

11. The method of claim 8 , wherein the importance of the criteria is increased based on a predicted main store access penalty resulting from a secondary cache miss in response to a request for the second logical block address.

12. The method of claim 8 , further comprising maintaining a plurality of data structures each associated with a logical block address range, wherein each of the data structures stores indicators indicative of the recent operations affecting the associated logical block address range, the indicators used to determine the criteria associated with the first logical block address.

13. The method of claim 8 , further comprising maintaining a plurality of data structures each associated with a time range, wherein each of the data structures stores indicators indicative of spatial locality of logical block address range, the indicators used to determine the criteria associated with the first logical block address.

14. An apparatus, comprising:
a main storage;
a secondary non-volatile cache that stores read-only data and mirrors a portion of data of the main storage;
a host interface configured to couple the apparatus to a host; and
a processor coupled to the main storage, the secondary non-volatile cache, and the host interface, the processor configured to:
track read operations of the host interface, the read operations affecting a first logical block address;
determine criteria associated with the read operations, the criteria being indicative of future read requests of a second logical block address associated with the first logical block address and wherein an importance of the criteria is reduced based on write activity associated with the first logical block address; and
cause data of at least the second logical block address from the main storage to be copied to the secondary non-volatile cache if the criteria meets a threshold.

15. The apparatus of claim 14 , wherein the criteria is indicative of at least one of a recent proximity in time of the host read operations and a closeness of address values of the host read operations.

16. The apparatus of claim 14 , wherein the processor further maintains a plurality of data structures each associated with a logical block address range, wherein each of the data structures stores indicators indicative of the recent operations affecting the associated logical block address range, the indicators used to determine the criteria associated with the first logical block address.

17. The apparatus of claim 14 , wherein the processor further maintains a plurality of data structures each associated with a time range, wherein each of the data structures stores indicators indicative of spatial locality of a logical block address range, the indicators used to determine the criteria associated with the first logical block address.

Assignees

• Sawin James David
• Friendshuh Luke W
• Jannyavula Venkata Sumanth
• Goss Ryan James
• Gaertner Mark Allen
• Seagate Technology Llc

Inventors

• Sawin James David
• Friendshuh Luke W
• Jannyavula Venkata Sumanth
• Goss Ryan James
• Gaertner Mark Allen

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F3/068

  Hybrid storage device · CPC title