Hardware acceleration of a write-buffering software transactional memory

Patent metadata

Field	Value
Publication number	US-9594565-B2
Application number	US-201213471841-A
Country	US
Kind code	B2
Filing date	Aug 1, 2012
Priority date	Apr 9, 2007
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.

First claim

What is claimed is:

1. A method comprising:
encountering a first read instruction in a first transaction, the first read instruction referencing a first address; and
in response to encountering the first read instruction:
checking an attribute field associated with a first memory line in a memory, wherein the first address is associated with the first memory line;
determining if the first address has been modified during execution of the first transaction based on the attribute field; and
reading a first value from the first memory line without searching a write space associated with the first transaction, in response to determining the first address has not been modified during execution of the first transaction; and
reading a write value from the software maintained write space associated with the first transaction, in response to determining the first address has been modified during execution of the first transaction.

2. The method of claim 1 , wherein the attribute field comprises a first and a second bit, and wherein determining if the first address location has been modified during execution of the first transaction based on the attribute field comprises:
checking the first bit;
determining the first address location has not been modified during execution of the first transaction, in response to the first bit being in a first logical state;
checking the second bit, in response to the first bit being in a second logical state;
determining the first address location has been modified during execution of the first transaction, in response to the second bit being in the second logical state.

3. The method of claim 2 , further comprising:
determining a miss to the memory line has occurred after checking the second bit, in response to the second bit being in the first logical state.

4. The method of claim 3 , further comprising, in response to the second bit being in the first logical state,
bringing a new value to the memory line of memory to service the miss;
determining if a write log entry associated with the first address exists, the write log to include a write value;
returning the write value in response to determining the write log entry exists; and
returning the new value in response to determining the write log entry does not exist.

5. The method of claim 2 , further comprising: reading a write log value from the write log associated with the first transaction, in response to determining the first address has been modified during execution of the first transaction.

6. The method of claim 2 , further comprising:
detecting a first write instruction in the first transaction; in response to detecting the first write instruction:
storing a write log value in the write log associated with the first transaction;
updating the first bit to the first logical state;
updating the second bit to the second logical state.

7. The method of claim 6 , further comprising:
committing the first transaction, wherein committing the first transaction comprises:
determining if a plurality of read instructions in the first transaction, including the read instruction, are valid;
acquiring a plurality of write locks for a plurality of addresses to be modified including the first address;
copying a plurality of write values from the write log to a plurality of memory lines in the memory, including the write log value from the write log to the memory line, in response to determining the plurality of read instructions are valid; and
releasing the plurality of write locks.

Assignees

• Saha Bratin
• Adl-Tabatabai Ali-Reza
• Jacobson Quinn
• Intel Corp

Inventors

• Saha Bratin
• Adl-Tabatabai Ali-Reza
• Jacobson Quinn

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title