Method for forming pattern and catalyst and electronic element using method therefor

Patent metadata

Field	Value
Publication number	US-9593427-B2
Application number	US-201314651903-A
Country	US
Kind code	B2
Filing date	Jul 25, 2013
Priority date	Jul 11, 2013
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Provided are a method for forming a pattern, and a catalyst and an electronic element using the method. The method for forming a pattern comprises the steps of: preparing, on a surface, a substrate sequentially including a photoconductive material layer and an oxide layer; making an area, on which a pattern is to be formed, on the oxide layer of the substrate, come into contact with an electrolyte; connecting the substrate and the electrolyte to a first electrode and a second electrode connected to a power source, respectively; and selectively irradiating light from a light source to the electrolyte and applying a voltage to the first electrode or the second electrode, thereby directly forming the pattern on the oxide layer of the substrate.

First claim

The invention claimed is:

1. A method for forming a pattern, the method comprising:
disposing a substrate on a piezoelectric stage;
preparing the substrate sequentially including a photoconductive material layer and an oxide layer on a surface of the substrate; where the photoconductive material layer comprises at least one selected from hydrogenated amorphous silicon (a-Si:H), amorphous germanium, hydrogenated amorphous germanium/silicon (a-Ge:H/a-Si—H), amorphous selenium (a-Se), amorphous gallium (a-Ga), amorphous hematite, and amorphous titanium oxide;
contacting an area on the oxide layer of the substrate on which a pattern is to be formed with an electrolyte;
connecting the substrate and the electrolyte to a first electrode and a second electrode connected to a power source, respectively;
irradiating light from a light source onto the electrolyte and onto the area on the oxide layer of the substrate on which the pattern is to be formed; and
applying a voltage to the first electrode or the second electrode to form the pattern directly on the oxide layer of the substrate,
wherein the pattern comprises at least one selected from Pt, MoO y S z (where, 0≦y≦1, 1.9≦z≦2.1) and CdSe,
wherein the oxide layer is a native oxide layer formed directly on an upper surface of the photoconductive material layer.

2. The method of claim 1 , wherein the photoconductive material layer comprises a first photoconductive material layer of a p-type or an n-type and a second photoconductive material layer of an intrinsic-type (i-type).

3. The method of claim 2 , wherein the photoconductive material layer further comprises a third photoconductive material layer of an n-type or a p-type.

4. The method of claim 1 , wherein a thickness of the photoconductive material layer is in a range of about 200 nm to about 900 nm.

5. The method of claim 2 , wherein a thickness of the first photoconductive material layer is in a range of about 10 nm to about 30 nm.

6. The method of claim 2 , wherein a thickness of the second photoconductive material layer is in a range of about 200 nm to about 700 nm.

7. The method of claim 3 , wherein a thickness of the third photoconductive material layer is in a range of about 50 nm to about 150 nm.

8. The method of claim 1 , wherein the substrate is a conductive substrate.

9. The method of claim 1 , wherein the substrate comprises metal, crystalline silicon, or indium tin oxide (ITO).

10. The method of claim 1 , wherein a thickness of the substrate is in a range of about 100 nm to about 500 nm.

11. The method of claim 1 , wherein a thickness of the oxide layer is in a range of about 0.1 nm to about 3 nm.

12. The method of claim 1 , wherein the electrolyte comprises at least one selected from a Pt precursor, a MoO y S z (where, 0≦y≦1 and 1.9≦z≦2.1) precursor, a CdSe precursor, and a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) precursor.

13. The method of claim 1 , wherein a pH of the electrolyte is in a range of about 4 to about 7.

14. The method of claim 1 , wherein the light source is one selected from a laser, a digital micromirror device (DMD), a liquid crystal display (LCD), a plasma display panel (PDP), a light-emitting diode (LED), and an organic light-emitting diode (OLED).

15. The method of claim 1 , wherein a range of the applied voltage is in a range of about −0.7 V to about −0.4 V vs. an Ag/AgCl electrode.

16. An electronic element prepared by using the method of claim 1 .

17. The electronic element of claim 16 , wherein the electronic element comprises an LED display, a solar cell, or a biosensor.

Assignees

• Snu R&Db Foundation
• Global Frontier Ct Multiscale Energy Systems

Inventors

• Chung Taek Dong
• Lim Sung Yul

Classifications

• H10P14/3431

  Selenides · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10P14/265

  using solutions · CPC title

• C25D17/10

  Electrodes {, e.g. composition, counter electrode} · CPC title