Frequency matched sub-sample feedforward modulation in amplitute level control loop
US-12316324-B2 · May 27, 2025 · US
US9590645B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9590645-B2 |
| Application number | US-201514816448-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 3, 2015 |
| Priority date | Feb 21, 2012 |
| Publication date | Mar 7, 2017 |
| Grant date | Mar 7, 2017 |
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An apparatus for PLL bandwidth expansion including a compensation filter and a phase locked loop, where the compensation filter is programmed with a compensation function derived based on programmable coefficients and parameters of a transmitting device, a frequency response of the phase locked loop, and a wanted frequency response.
Opening claim text (preview).
What is claimed is: 1. An apparatus for phase locked loop (“PLL”) bandwidth expansion comprising: a transmitting device including a programmable hardware compensation filter configured to receive a transmitted signal and output a filtered signal, and a PLL circuit installed in front of the compensation filter and configured to receive the filtered signal and output a modulated carrier signal, the programmable hardware compensation filter configured to be programmed with a compensation function having filter coefficients, wherein the filter coefficients are determined from programmable coefficients and parameters stored on the transmitting device, and wherein a function of the programmable hardware compensation filter (“Fcomp(s)”) is: Fcomp ( s ) = y 0 · ( s 5 + s 4 · x 4 + s 3 · x 3 + s 2 · x 2 + s · x 1 + x 0 ) x 1 · ( s 5 + s 4 · z 4 + s 3 · z 3 + s 2 · z 2 + s · z 1 + z 0 ) , where x 0 = a · K ϕ A · b · w n 2 · K vco N x 1 = K ϕ A · b · w n 2 · K vco N x 2 = w n 2 · b , x 3 = w n 2 + 2 ξ · w n · b x 4 = w n 2 + 2 ξ
Details of the phase-locked loop · CPC title
Modifications of modulator to linearise modulation, e.g. by feedback, and clearly applicable to more than one type of modulator · CPC title
for assuring initial synchronisation or for broadening the capture range · CPC title
using a phase locked loop · CPC title
modulating the reference clock · CPC title
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