Logical elements with switchable connections

Patent metadata

Field	Value
Publication number	US-9590629-B2
Application number	US-201414530624-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Nov 2, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers.

First claim

What is claimed is:

1. An apparatus for data manipulation comprising:
a plurality of logical elements;
configurable connections between the plurality of logical elements; and
a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of circular buffers contain configuration instructions which control different configurable connections between the plurality of logical elements and dynamically change operation of the logical elements per cycle based on the rotating of the circular buffer and wherein the configuration instructions are pre-processed by a compiler and statically scheduled to avoid collisions among the plurality of logical elements.

2. The apparatus of claim 1 wherein the plurality of logical elements comprise one or more of switching elements, processing elements, or storage elements.

3. The apparatus of claim 1 wherein the plurality of circular buffers have differing lengths.

4. The apparatus of claim 3 wherein the plurality of circular buffers having differing lengths resynchronize with a zeroth pipeline stage for each of the plurality of circular buffers.

5. The apparatus of claim 1 wherein the configurable connections comprise a switching fabric.

6. The apparatus of claim 5 wherein the switching fabric includes fan-in and fan-out connections.

7. The apparatus of claim 1 wherein the configurable connections are time multiplexed.

8. The apparatus of claim 1 wherein the circular buffer is programmed and instructions are pre-processed to generate input to the circular buffer for dynamic programming.

9. The apparatus of claim 1 wherein the circular buffer controls passing data to a quad of processing elements through switching elements, where each of the quad of processing elements is controlled by four other circular buffers, where data is passed back through the switching elements from the quad of processing elements where the switching elements are again controlled by the circular buffer.

10. The apparatus of claim 1 wherein a column within the circular buffer can be skipped in a cycle.

11. The apparatus of claim 10 wherein not skipping indicates a valid instruction.

12. The apparatus of claim 1 wherein the plurality of logical elements includes a processing element that can be placed in a sleep state where the sleep state is exited based on data being valid.

13. The apparatus of claim 12 wherein the sleep state can be entered by an instruction within the processing element.

14. The apparatus of claim 13 wherein the sleep state can only be exited by stimulus external to the processing element and not based on programming of the processing element.

15. The apparatus of claim 14 wherein the sleep state is exited based on an instruction applied to a switching fabric.

16. The apparatus of claim 1 wherein the circular buffer comprises a plurality of switch instructions for the configurable connections.

17. The apparatus of claim 16 wherein the circular buffer comprises a plurality of switch instructions per cycle for the configurable connections.

18. The apparatus of claim 1 wherein the configurable connections provide three-dimensional routing.

19. The apparatus of claim 1 further comprising storage elements coupled to the configurable connections.

20. The apparatus of claim 19 wherein the storage elements store data while the configurable connections are busy with other data.

21. The apparatus of claim 1 wherein the configurable connections enable bypassing of neighboring logical elements.

22. The apparatus of claim 1 wherein the configurable connections comprise one or more of a fan-in, a fan-out, or a local storage.

23. The apparatus of claim 1 wherein the configurable connections route through one or more of silicon vias, two-dimensional connections, three-dimensional connections, or greater-than three-dimensional connections.

24. The apparatus of claim 1 wherein communication through the configurable connections is based on data being valid.

25. A computer-implemented method of logic implementation comprising:
designing a switching fabric using:
a plurality of logical elements;
configurable connections between the plurality of logical elements; and
a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of circular buffers contain configuration instructions which control different configurable connections between the plurality of logical elements and dynamically change operation of the logical elements per cycle based on the rotating of the circular buffer and wherein the configuration instructions are pre-processed by a compiler and statically scheduled to avoid collisions among the plurality of logical elements.

26. A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus, the computer program product comprising code which causes one or more processors to perform operations of:
designing a switching fabric using:
a plurality of logical elements;
configurable connections between the plurality of logical elements; and
a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of circular buffers contain configuration instructions which control different configurable connections between the plurality of logical elements and dynamically change operation of the logical elements per cycle based on the rotating of the circular buffer and wherein the configuration instructions are pre-processed by a compiler and statically scheduled to avoid collisions among the plurality of logical elements.

27. The apparatus of claim 1 wherein the preprocessing inserts further instructions to prevent the collision.

28. The apparatus of claim 27 wherein the further instructions include one or more of a group of storage instructions, sleep instructions, and no-op instructions.

29. The apparatus of claim 1 further comprising replacing multiple instructions with a single fan-in instruction in the pre-processing.

30. The apparatus of claim 1 further comprising clusters of one or more processing elements, storage elements, and switching elements.

31. The apparatus of claim 30 wherein an additional circular buffer is implemented for each processing element.

32. The apparatus of claim 1 where collisions are avoided by intermediate data being stored in registers for pipeline cycles before being sent to an output port for a cluster.

33. The apparatus of claim 12 wherein the processing element wakes up from the sleep state when valid data is applied to inputs of the processing element.

Assignees

• Wave Semiconductor Inc
• Wave Computing Inc

Inventors

• Nicol Christopher John

Classifications

• H03K19/017581 Primary

  programmable · CPC title

• H03K19/1776

  for memories · CPC title

• H03K19/17764

  for reliability · CPC title