Decoupling capacitor and method of making same

Patent metadata

Field	Value
Publication number	US-9590119-B2
Application number	US-201213349723-A
Country	US
Kind code	B2
Filing date	Jan 13, 2012
Priority date	Jan 13, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A device comprises a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type. A contact structure is in direct contact with the first and second implant regions and the electrode. A third implant region has a second dopant type different from the first dopant type. A bulk contact is provided on the third implant.

First claim

What is claimed is:

1. A device, comprising:
a semiconductor substrate having first and second implant regions and an electrode above and between the first and second implant regions of a first dopant type;
a contact structure in direct contact with the first and second implant regions and the electrode; and
a third implant region having a second dopant type different from the first dopant type, the third implant having a bulk contact thereon,
wherein:
the contact structure includes at least one slot contact extending parallel to a channel length direction, and
the at least one slot contact is located outside of the first and second implant regions such that the at least one slot contact is positioned laterally from the first and second implant regions.

2. The device of claim 1 , wherein the device is a decoupling capacitor.

3. The device of claim 1 , wherein the slot contact directly contacts the electrode.

4. The device of claim 1 , wherein:
the contact structure includes a rectangle having a plurality of slot contacts;
a first one of the slot contacts directly contacts the first implant region;
a second one of the slot contacts directly contacts the second implant region; and
third and fourth contacts directly contact the electrode outside of the first and second implant regions.

5. The device of claim 1 , wherein the contact structure includes:
a first contact layer in direct contact with the first and second implant regions;
a second contact layer on the first contact layer; and
a contact portion on the electrode.

6. The device of claim 1 , wherein the device is included in a plurality of devices on the substrate, the plurality of devices arranged along a channel length direction; and
the third implant region and bulk contact extend lengthwise in the channel length direction along each of the plurality of devices.

7. The device of claim 1 , wherein:
the device is included in a plurality of devices on the substrate, the plurality of devices arranged perpendicular to a channel length direction;
the contact structure extends perpendicular to the channel length direction, and connects implant regions of the plurality of devices; and
the third implant region and bulk contact extend perpendicular to the channel length direction along each of the plurality of devices.

8. A method of making a capacitor, comprising:
forming an insulating layer and an electrode above and between first and second implant regions of a first dopant type in a surface of a semiconductor substrate;
forming a conductive contact structure on the first and second implant regions, the conductive structure having an additional portion overlying a portion of the electrode, and
forming a bulk contact on a third implant region in the surface, the third implant region having a different dopant type from the first dopant type,
wherein:
the contact structure includes at least one slot contact extending parallel to a channel length direction, and
the at least one slot contact is located outside of the first and second implant regions such that the at least one slot contact is positioned laterally from the first and second implant regions.

9. The method of claim 8 , wherein the step of forming the conductive contact structure includes:
forming first conductive contacts on the first and second implant regions; and
forming a continuous conductive second contact pattern on the first contacts and on the portion of the electrode.

10. The method of claim 9 , wherein the second contact pattern has a rectangle shape with a respective side of the rectangle overlying each respective one of the first and second implant regions.

11. The method of claim 10 , wherein the second conductive pattern has two sides which overlie respective portions of the electrode.

12. The method of claim 9 , wherein the first conductive contacts are formed of tungsten and the second contact layer is formed of tungsten or copper.

13. The method of claim 8 , wherein the step of forming the conductive contact structure includes:
forming a first dielectric layer over the substrate and the electrode layer;
forming first and second slot contact vias in the first dielectric layer, extending to the first and second implant regions, respectively;
forming at least a third slot contact via in the first dielectric layer extending to a top of the electrode;
filling the first, second and third slot contact vias with a conductive material capable of forming an ohmic contact with a semiconductor material.

14. The method of claim 13 , wherein the step of forming the bulk contact includes:
forming a fourth slot contact in the first dielectric layer, extending to the third implant region at the same time the first and second slot contact vias are formed; and
filling the fourth slot contact via with the conductive material at the same time the first, second, and third slot contact vias are filled.

15. The method of claim 14 , further comprising:
forming a second dielectric layer over the first, second, third and fourth slot contact vias; and
forming a first conductive line layer in the second dielectric layer as part of a front end of line process, the first conductive line layer having connections to the contact structure and the bulk contact.

Assignees

• Chen Chung-Hui
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chung-Hui

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L23/5223

  Electricity · mapped topic

• H01L27/0288

  Electricity · mapped topic

• H01L29/94 Primary

  Electricity · mapped topic