Semiconductor devices having multiple gate structures and methods of manufacturing such devices

Patent metadata

Field	Value
Publication number	US-9590103-B2
Application number	US-201614990863-A
Country	US
Kind code	B2
Filing date	Jan 8, 2016
Priority date	May 21, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance;
a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance;
a plurality of first spacers on sidewalls of the respective first gate structures;
a dielectric layer on outer sidewalls of the respective first spacers;
a plurality of second spacers on sidewalls of the respective second gate structures; and
a plurality of third spacers on outer sidewalls of the respective second spacers,
wherein a sum of a first thickness of a first of the first spacers and a second thickness of the dielectric layer that are on a sidewall of a first of the first gate structures is substantially equal to a sum of a third thickness of a first of the second spacers and a fourth thickness of a first of the third spacers that are on a sidewall of a first of the second gate structures.

2. The semiconductor device of claim 1 , wherein the first thickness of the first of the first spacers is substantially equal to the third thickness of the first of the second spacers; and
wherein the second thickness of the dielectric layer is substantially equal to the fourth thickness of the first of the third spacers.

3. The semiconductor device of claim 1 , wherein the first distance is substantially equal to the second distance; and
wherein a first gap that is between portions of the dielectric layer that are on facing sidewalls of an adjacent pair of the first gate structures is substantially equal to a second gap between the third spacers that are on facing sidewalls of an adjacent pair of the second gate structures.

4. The semiconductor device of claim 3 , further comprising an etch stop layer on sidewalls of the dielectric layer and the third spacers,
wherein a third gap between portions of the etch stop layer that axe on facing sidewalls of the adjacent pair of the first gate structures is substantially equal to a fourth gap between portions of the etch stop layer that are on facing sidewalls of the adjacent pair of the second gate structures.

5. The semiconductor device of claim 1 , further comprising at least a first active fin that extends in a first direction in the first region to cross under the first gate structures;
wherein the first spacers have an L-shaped cross-section.

6. The semiconductor device of claim 5 , wherein the first of the first spacers has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate, a length of the parallel portion in the first direction being substantially equal to or greater than the sum of the first thickness and the second thickness.

7. The semiconductor device of claim 1 , further comprising a plurality of first embedded source/drain regions on opposed sides of the first gate structures,
wherein the dielectric layer covers upper surfaces of the first embedded source/drain regions.

8. The semiconductor device of claim 5 , further comprising at least a second active fin that extends in the first direction in the second region to cross under the second gate structures;
wherein the second spacers have an L-shaped cross-section.

9. The semiconductor device of claim 8 , wherein the first of the second spacers has a parallel portion and a perpendicular portion with respect to an upper surface of the substrate, a length of the parallel portion in the first direction being greater than the sum of the third thickness and the fourth thickness.

10. The semiconductor device of claim 8 , wherein the third spacers have an L-shaped cross-section.

11. The semiconductor device of claim 1 , further comprising a plurality of second embedded source/drain regions on opposed sides of the second gate structures,
wherein the second embedded source/drain regions comprise silicon germanium (SiGe) doped with a P-type impurity.

12. The semiconductor device of claim 11 , wherein the second embedded source/drain regions include a plurality of regions having different germanium (Ge) concentration from each other.

13. A semiconductor device, comprising:
a substrate having a first region and a second region, the first region including a plurality of first active fins and the second region including a plurality of second active fins;
a plurality of first gate structures that cross over the first active fins in the first region, the first gate structures being spaced apart from each other by a first distance;
a plurality of first embedded source/drain regions on opposed sides of the first gate structures;
a plurality of first spacers that have L-shaped cross-sections on sidewalls of the respective first gate structures;
a dielectric layer on outer sidewalls of the first spacers and on upper surfaces of the first embedded source/drain regions;
a plurality of second gate structures that cross over the second active fins in the second region, the second gate structures being spaced apart from each other by a second distance;
a plurality of second embedded source/drain regions on opposed sides of the second gate structures;
a plurality of second spacers that have L-shaped cross-sections on sidewalls of the respective second gate structures; and
a plurality of third spacers that have L-shaped cross-sections on outer sidewalls of the second spacers.

14. The semiconductor device of claim 13 , wherein a sum of a first thickness of a first of the first spacers that is on a first of the first gate structures and a second thickness of the dielectric layer that is on a sidewall of the first of the first gate structures is substantially equal to a sum of a third thickness of a first of the second spacers that is on a first of the second gate structures and a fourth thickness of a first of the third spacers that is on a sidewall of the first of the second spacers.

15. A semiconductor device, comprising:
a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a first active fin extending in the first direction in a first region of the substrate;
a first gate structure that crosses over the first active fin in the first region of the substrate;
a first embedded source/drain region on a first side of the first gate structure;
a pair of first spacers having respective inner sidewalk that are directly on respective opposed sidewalls of the first gate structure, each of the first spacers including a first portion that extends in the first direction and a second portion that extends in a third direction that is perpendicular to both the first direction and the second direction;
a dielectric layer that comprises a material different from a material of the first spacers directly on outer sidewalls of the respective first spacers;
a second active fin extending in the first direction in a second region of the substrate;
a second gate structure that crosses over the second active fin in the second region of the substrate;
a second embedded source/drain region on a first side of the second gate structure;
a pair of second spacers having respective inner sidewalls that are directly on respective opposed sidewalls of the second gate structure, each of the second spacers including a first portion that extends in the first direction and a second portion that extends in the third direction;
a pair of third spacers that comprises a material different from a material of the

Assignees

• Kim Yoon Hae
• Lee Jin Wook
• Jung Jong Ki
• Kang Myung Ii
• Yang Kwang Yong
• Lee Kwan Heum
• Lee Byeong Chan
• Samsung Electronics Co Ltd

Inventors

• Kim Yoon Hae
• Lee Jin Wook
• Jung Jong Ki
• Kang Myung Ii
• Yang Kwang Yong
• Lee Kwan Heum
• Lee Byeong Chan

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic