Semiconductor device

Patent metadata

Field	Value
Publication number	US-9590075-B2
Application number	US-201414164853-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Jan 9, 2007
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor drain layer of a first conductivity type;
a semiconductor drift layer of a second conductivity type overlying the semiconductor layer of the first conductivity type;
a second-conductivity-type body layer overlying the semiconductor layer of the second conductivity type;
a plurality of trenches extending into the semiconductor body and drift layers, wherein each of the plurality of trenches comprises a first dielectric material disposed therein, the first dielectric material including an intentionally introduced fixed charge;
a plurality of control gates coupled to the body layer to control conduction therethrough; and
a plurality of first-conductivity-type source regions coupled to the semiconductor body layer of the second conductivity type;
wherein said intentionally introduced fixed charge at least partially balances the net charge in depleted portions of the semiconductor drift layer in the OFF state.

2. The semiconductor device of claim 1 wherein the electrical characteristic of the semiconductor device comprises a breakdown voltage.

3. The semiconductor device of claim 1 wherein an integrated charge density of a dopant measured along a line perpendicular to the first thickness between two adjacent ones of said trenches ranges from about q*1×10 12 /cm 2 to about q*5×10 12 /cm 2 .

4. The semiconductor device of claim 1 wherein the control gate comprises a control gate trench extending a third predetermined distance toward the semiconductor layer of the first conductivity type.

5. The semiconductor device of claim 4 wherein the control gate trench further comprises a polysilicon material disposed interior to the dielectric material.

6. The semiconductor device of claim 4 wherein the plurality of trenches further comprises a second material disposed interior to the dielectric material.

7. The semiconductor device of claim 6 further comprising a second dielectric material disposed interior to the second material.

8. The semiconductor device of claim 1 wherein the control gate comprises a gate material disposed as a planar structure on the semiconductor layer of the second conductivity type.

9. The semiconductor device of claim 1 wherein a diffused region is formed adjacent to the pair of trenches.

10. The semiconductor device of claim 1 wherein the dielectric material comprises a silicon oxide material.

11. The semiconductor device of claim 1 further comprising a third dielectric material disposed on the pair of trenches.

12. The semiconductor device of claim 1 further comprising at least one termination trench extending through the body layer and the semiconductor drift layer.

13. The semiconductor device of claim 1 , wherein the intentionally introduced charge comprises cesium.

14. A semiconductor device comprising:
a semiconductor drain layer of a first conductivity type;
a semiconductor drift layer overlying the drain layer, and including a first set of pillars having the first conductivity type and a second set of pillars having a second conductivity type
a plurality of trenches extending into the drift layer, wherein each of the plurality of trenches comprises a first dielectric material disposed therein, the first dielectric material including an intentionally introduced fixed charge;
a plurality of control gates capacitively coupled to a plurality of second-conductivity-type body regions to control conduction therethrough; and
a plurality of first-conductivity-type source regions coupled to the body region;
wherein said intentionally introduced fixed charge at least partially balances the net charge in depleted portions of the second pillars.

15. The semiconductor device of claim 14 , wherein the intentionally introduced charge comprises cesium.

Assignees

• Maxpower Semiconductor Inc

Inventors

• Darwish Mohamed N

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/225

  of a molecular ion, e.g. decaborane · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title