Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Patent metadata

Field	Value
Publication number	US-9590069-B2
Application number	US-201514752365-A
Country	US
Kind code	B2
Filing date	Jun 26, 2015
Priority date	Sep 28, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

First claim

What is claimed is:

1. A method of forming an asymmetric high electron mobility transistor (HEMT), the method comprising:
depositing a sacrificial material over a substrate comprising a group III-N channel layer;
etching at least one trench to form a mandrel of the sacrificial material spaced apart by a first length and a second length, different from the first, from peripheral regions of the sacrificial material;
conformally depositing a dielectric liner into the at least one trench and over the mandrel;
depositing a bulk dielectric over the dielectric liner to fill the at least one trench;
etching through the bulk dielectric and dielectric liner to expose the peripheral regions of the sacrificial material;
etching the peripheral regions of the sacrificial material selectively to the dielectric liner to expose a semiconductor channel layer disposed at the periphery of the at least one trench;
forming semiconductor source and drain regions in contact with the exposed semiconductor channel layer;
etching through the bulk dielectric and dielectric liner to expose the mandrel;
and replacing the mandrel with a gate stack.

2. The method of claim 1 , wherein depositing the sacrificial material
further comprises depositing a dielectric, wherein conformally depositing the dielectric liner further comprises depositing a material including a metal oxide, and wherein depositing the bulk dielectric further comprises depositing a dielectric with a lower dielectric constant than that of the dielectric liner.

3. The method of claim 2 , wherein etching through the bulk dielectric and dielectric liner further comprises:
masking a region encompassing the mandrel and at least a portion of the at least one trench; and
anisotropically etching the bulk dielectric and dielectric liner unprotected by the masking.

4. The method of claim 3 , wherein etching the peripheral regions of the sacrificial material to expose a semiconductor channel layer further comprises:
isotropically etching the sacrificial material;
etching a semiconductor barrier layer disposed over the channel layer; and
recessing the channel layer surface with an isotropic etch to undercut an interfacial layer of the channel layer in contact with the barrier layer.

5. The method of claim 1 , wherein forming the semiconductor source and drain regions further comprises conformally growing a heavily n-type doped III-N material with a metalorganic precursor.

6. The method of claim 5 , wherein the heavily doped III-N material comprises InGaN doped to at least 1e19 cm −3 .

7. The method of claim 1 , wherein etching through the bulk dielectric and dielectric liner to expose the mandrel further comprises anisotropically etching a portion of the bulk dielectric and dielectric liner disposed over the mandrel; and
wherein replacing the mandrel with a gate stack further comprises:
etching the sacrificial material selectively to the dielectric liner to expose and underlying semiconductor layer;
conformally depositing a gate dielectric layer over the channel layer and over the dielectric liner; and
depositing a gate metal over the gate dielectric layer.

8. The method of claim 1 , further comprising doping a semiconductor barrier layer disposed over the channel layer with fluorine by implantation or exposure to a plasma of a fluorinated source gas.

9. The method of claim 8 , wherein replacing the mandrel with a gate stack further comprises:
etching the sacrificial material selectively to the dielectric liner to expose the semiconductor barrier layer;
conformally depositing a base gate dielectric layer directly on the fluorine doped semiconductor barrier layer;
conformally depositing a top gate dielectric layer directly on the base gate dielectric layer; and
depositing a gate metal over the top gate dielectric layer.

10. A method of forming a high electron mobility transistor (HEMT), the method comprising:
forming a source region and a drain region in contact with a III-N semiconductor channel region disposed over a substrate;
fluorine doping a semiconductor barrier layer disposed on the channel region;
depositing a gate dielectric over the barrier layer, wherein depositing the gate dielectric comprises:
conformally depositing a base gate dielectric layer onto the barrier layer at a first temperature; and
conformally depositing a top gate dielectric layer onto the base gate dielectric layer at a second temperature, higher than the first; and

depositing a gate electrode over the gate dielectric.

11. The method of claim 10 , wherein the fluorine doping further comprises fluorine doping at least a portion of the barrier layer to between 1e17 and 1e18 cm −3 .

12. The method of claim 10 , wherein the fluorine doping further comprises:
implanting or exposing the semiconductor barrier layer to a plasma of a fluorinated source gas.

13. The method of claim 12 , wherein the fluorine doping comprises exposing the semiconductor to a plasma of a fluorinated source gas.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Radosavljevic Marko
• Mukherjee Niloy
• Goel Niti
• Gardner Sanaz Kabehie
• Sung Seung Hoon
• Pillarisetty Ravi
• Chau Robert S

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P32/1204

  from a plasma phase · CPC title

• H10P32/174

  being Group III-V material · CPC title