Three-dimensional semiconductor template for making high efficiency solar cells

US9590035B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9590035-B2
Application numberUS-201414195748-A
CountryUS
Kind codeB2
Filing dateMar 3, 2014
Priority dateNov 13, 2008
Publication dateMar 7, 2017
Grant dateMar 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabrication of a three-dimensional silicon template, the method comprising: forming a patterned mask on a silicon template surface defining a pattern of base openings, said pattern of base openings comprising a pattern of at least two differently sized base openings; selectively removing silicon material from said silicon template in said base openings to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls each aligned along a (111) crystallographic plane of the silicon template wherein said walls define inverted pyramidal cavities, said inverted pyramidal cavities comprising at least two differently sized inverted pyramidal cavities, said removal of silicon material comprising the steps of: anisotropically etching the silicon template to form a plurality of walls each aligned along a (111) crystallographic plane of the silicon template wherein said walls form an inverted pyramidal cavity. 2. The method of claim 1 , wherein said step of anisotropically etching the silicon template utilizes KOH or NaOH as an etchant. 3. The method of claim 1 , wherein said step of anisotropically etching the silicon template utilizes TetraMethyl-Ammonium-Hydroxide (TMAH) as an etchant. 4. The method of claim 1 , wherein said patterned base openings of said patterned mask is a staggered pattern of at least two differently sized base openings. 5. The method of claim 1 , wherein said patterned mask is SiO 2 . 6. The method of claim 1 , wherein said patterned mask is SiN.

Assignees

Inventors

Classifications

  • of Group IV materials · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Shape defined by a solid member other than seed or product [e.g., Bridgman-Stockbarger] · CPC title

  • Monocrystalline silicon PV cells · CPC title

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Frequently asked questions

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What does patent US9590035B2 cover?
A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallog…
Who is the assignee on this patent?
Solexel Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/0657. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).