Thin-film transistor, manufacturing method thereof, display substrate and display device

Patent metadata

Field	Value
Publication number	US-9589991-B2
Application number	US-201414769180-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	Aug 28, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A thin-film transistor (TFT), a manufacturing method thereof, display substrate and a display device are disclosed. The TFT includes: an active layer, gate insulating layer, gate electrode, interlayer dielectric layer, source electrode and a drain electrode disposed on a base substrate in sequence. The source electrode and drain electrode are respectively connected with the active layer via a through hole exposing the active layer; the gate insulating layer at least includes a silicon oxide layer and a silicon nitride layer in a two-layer structure; the interlayer dielectric layer at least includes silicon oxide layers and silicon nitride layers in a four-layer structure; the silicon oxide layers and silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and the dimension of one side of the through hole away from the base substrate is greater than that of one side close to the base substrate.

First claim

The invention claimed is:

1. A method for manufacturing a thin-film transistor (TFT), the TFT comprising an active layer, a gate insulating layer, a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode disposed on a base substrate in sequence, the gate insulating layer at least comprising a silicon oxide layer and a silicon nitride layer in a two-layer structure, the interlayer dielectric layer at least comprising silicon oxide layers and silicon nitride layers in a four-layer structure, all the silicon oxide layers and all the silicon nitride layers of the gate insulating layer and the interlayer dielectric layer being alternately arranged, the manufacturing method comprising:
alternately depositing the silicon oxide layers and the silicon nitride layers on the base substrate in a process of respectively forming the gate insulating layer and the interlayer dielectric layer, and
adjusting technological parameters so that compactness of at least odd-numbered layers or even-numbered layers in all the layers of the gate insulating layer and the interlayer dielectric layer is gradually increased as counted from the silicon oxide layer or the silicon nitride layer, farthest from the base substrate, in the interlayer dielectric layer.

2. The manufacturing method according to claim 1 , wherein the compactness of all the silicon oxide layers and all the silicon nitride layers of the gate insulating layer and the interlayer dielectric layer is gradually increased as counted from the silicon oxide layer or the silicon nitride layer, farthest from the base substrate, in the interlayer dielectric layer.

3. A thin-film transistor (TFT), comprising an active layer, a gate insulating layer, a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode disposed on a base substrate in sequence, the source electrode and the drain electrode being each connected with the active layer via a through hole exposing the active layer, both the gate insulating layer and the interlayer dielectric layer comprising silicon oxide layers and silicon nitride layers,
wherein the gate insulating layer comprises at least the silicon oxide layer and the silicon nitride layer in a two-layer structure;
the interlayer dielectric layer comprises at least the silicon oxide layers and the silicon nitride layers in a four-layer structure;
the silicon oxide layers and the silicon nitride layers of the gate insulating layer and the interlayer dielectric layer are alternately arranged; and
compactness of at least odd-numbered or even-numbered layers in all the layers of the gate insulating layer and the interlayer dielectric layer is gradually increased as counted from the silicon oxide layer or the silicon nitride layer, that is farthest from the base substrate, in the interlayer dielectric layer.

4. The TFT according to claim 3 , wherein the active layer comprises a source region, a drain region and a polysilicon region disposed between the source region and the drain region,
the source electrode and the drain electrode are respectively connected with the active layer via the through hole exposing the active layer,
the source electrode is connected with the source region via a second through hole exposing the source region, and
the drain electrode is connected with the drain region via a third through hole exposing the drain region.

5. The TFT according to claim 3 , wherein the compactness of all the silicon oxide layers and all the silicon nitride layers of the gate insulating layer and the interlayer dielectric layer is gradually increased as counted from the silicon oxide layer or the silicon nitride layer, that is farthest from the base substrate, in the interlayer dielectric layer.

6. The TFT according to claim 5 , wherein the active layer comprises a source region, a drain region and a polysilicon region disposed between the source region and the drain region,
the source electrode and the drain electrode are respectively connected with the active layer via the through hole exposing the active layer,
the source electrode is connected with the source region via a second through hole exposing the source region, and
the drain electrode is connected with the drain region via a third through hole exposing the drain region.

7. The TFT according to claim 5 , wherein an overall thickness of all the silicon oxide layers of the interlayer dielectric layer is from 100 nm to 300 nm;
an overall thickness of all the silicon nitride layers of the interlayer dielectric layer is from 200 nm to 500 nm; and
the interlayer dielectric layer comprises the silicon oxide layers and the silicon nitride layers in a four-layer or six-layer structure.

8. The TFT according to claim 7 , wherein the overall thickness of all the silicon oxide layers of the gate insulating layer is from 40 nm to 100 nm;
the overall thickness of all the silicon nitride layers of the gate insulating layer is from 40 nm to 100 nm; and
the gate insulating layer comprises the silicon oxide layers and the silicon nitride layers in a four-layer structure.

9. The TFT according to claim 3 , wherein an overall thickness of all the silicon oxide layers of the interlayer dielectric layer is from 100 nm to 300 nm;
an overall thickness of all the silicon nitride layers of the interlayer dielectric layer is from 200 nm to 500 nm; and
the interlayer dielectric layer comprises the silicon oxide layers and the silicon nitride layers in a four-layer or six-layer structure.

10. The TFT according to claim 9 , wherein the active layer comprises a source region, a drain region and a polysilicon region disposed between the source region and the drain region,
the source electrode and the drain electrode are respectively connected with the active layer via the through hole exposing the active layer,
the source electrode is connected with the source region via a second through hole exposing the source region, and
the drain electrode is connected with the drain region via a third through hole exposing the drain region.

11. The TFT according to claim 9 , wherein the overall thickness of all the silicon oxide layers of the gate insulating layer is from 40 nm to 100 nm;
the overall thickness of all the silicon nitride layers of the gate insulating layer is from 40 nm to 100 nm; and
the gate insulating layer comprises the silicon oxide layers and the silicon nitride layers in a four-layer structure.

12. The TFT according to claim 11 , wherein the active layer comprises a source region, a drain region and a polysilicon region disposed between the source region and the drain region,
the source electrode and the drain electrode are respectively connected with the active layer via the through hole exposing the active layer,
the source electrode is connected with the source region via a second through hole exposing the source region, and
the drain electrode is connected with the drain region via a third through hole exposing the drain region.

13. A display substrate, comprising the thin-film transistor (TFT) according to claim 1 .

14. The display substrate according to claim 13 , further comprising an anode electrically connected with the drain electrode, a cathode disposed on a side, of the anode, away from the TFT, and an organic material function layer disposed between the anode and the cathode.

15. A display device, comprising the display substrate according to claim 13 .

16. The display substrate according to claim 13 , further comprising a pixel electrode electrically connected with the drain electrode.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zuqiang
• Liu Chien Hung

Classifications

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H01L29/42384

  Electricity · mapped topic

• H01L29/786

  Electricity · mapped topic

• H01L27/12

  Electricity · mapped topic

• H01L29/42364

  Electricity · mapped topic