Combined QFN and QFP semiconductor package

Patent metadata

Field	Value
Publication number	US-9589928-B2
Application number	US-201414552497-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Apr 15, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a die pad having an upper surface and a lower surface;
an integrated circuit attached on the upper surface of the die pad;
a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;
a plurality of second package type leads that surround the first package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and
a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of first and second package type leads, and the first and second bond wires;
a pre-molded portion for positioning the first package type leads and supporting the second package type leads over the first package type leads, wherein the pre-molded portion includes a structure located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad, wherein the structure is formed separately from the mold cap.

2. The semiconductor package of claim 1 , wherein the second package type leads have intermediate portions that project from sides of the mold cap and distal ends that lie in a parallel plane with the first package type leads.

3. The semiconductor package of claim 2 , wherein a lower surface of the die pad not covered by the mold cap is exposed.

4. The semiconductor package of claim 2 , wherein a lower surface of the die pad is covered by the mold cap.

5. The semiconductor package of claim 1 , wherein the plurality of the first package type leads are of a lead type for a quad flat non-leaded package (QFN) and the plurality of the second package type leads are of a lead type for a quad flat package (QFP).

6. The semiconductor package of claim 1 , further comprising a ground ring surrounded by the first package type leads and electrically coupled to the integrated circuit.

7. The semiconductor package of claim 1 , further comprising a power ring surrounded by the first package type leads and electrically coupled to the integrated circuit.

8. The semiconductor package of claim 1 , wherein the second package type leads are attached to the pre-molded portion with adhesive.

9. The semiconductor package of claim 1 , further comprising an adhesive attaching leads of the plurality of second package type leads to the structure of the pre-molded portion.

10. The semiconductor package of claim 1 , wherein the structure includes a plastic material.

11. The semiconductor package of claim 1 , wherein the structure includes an encapsulant material.

12. The semiconductor package of claim 1 , wherein the structure includes tape.

13. The semiconductor package of claim 1 wherein at least a portion of each lead of the plurality of first package type leads is encapsulated in the pre-molded portion.

14. The semiconductor package of claim 1 wherein a lower portion of the pre-molded portion not covered by the mold cap is exposed.

15. The semiconductor package of claim 1 wherein the pre-molded portion includes an opening, wherein the die pad is located in an area of the opening.

16. A semiconductor package, comprising:
a die pad having an upper surface and a lower surface;
an integrated circuit attached on the upper surface of the die pad;
a pre-molded assembly comprising a plurality of first package type leads and mold material, wherein at least a portion of each lead of the plurality of first package type leads is encapsulated in the mold material, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;
a plurality of second package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and
a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of second package type leads, the pre-molded assembly, and the first and second bond wires, wherein the mold cap and the mold material are separately formed;
wherein mold material of the pre-molded assembly is located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad.

17. The semiconductor package of claim 16 , wherein the second package type leads are attached to the pre-molded assembly with adhesive.

18. The semiconductor package of claim 16 wherein the pre-molded assembly includes an opening, wherein the die pad is located in an area of the opening.

19. A semiconductor package, comprising:
a die pad having an upper surface and a lower surface;
an integrated circuit attached on the upper surface of the die pad;
a pre-molded assembly comprising a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;
a plurality of second package type leads that surround the first package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and
a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of second package type leads, the pre-molded assembly, and the first and second bond wires;
wherein a structure of the pre-molded assembly is located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad, wherein the structure is of a material different than a material of the mold cap.

Assignees

• Bai Zhigang
• Yao Jinzhong
• Tan Lan Chu
• Nxp Usa Inc

Inventors

• Bai Zhigang
• Yao Jinzhong
• Tan Lan Chu

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title