Interconnect arrangement for hexagonal attachment configurations

Patent metadata

Field	Value
Publication number	US-9589919-B2
Application number	US-201113993334-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for signal nodes and ground nodes which utilizes the cross-talk reduction by cancellation property of geometrically symmetry and orthogonality to reduce signal node to ground node ratio for increasing signaling density.

First claim

What is claimed is:

1. A device comprising: a plurality of interconnects arranged in a hexagonal node configuration including a plurality of nodes each neighboring a respective other of the plurality of nodes, the plurality of nodes each at substantially a same distance from a respective one or more neighboring nodes of the plurality of nodes, wherein, for each node of the plurality of nodes: the node is: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; or a ground node; and the node neighbors six other nodes each selected from a respective group consisting of: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; and a ground node; wherein the plurality of nodes includes: differential signal node pairs each arranged along a respective row of substantially parallel rows of the hexagonal node configuration, the differential signal node pairs including a first differential signal node pair and a second differential signal node pair each in arranged along a first row; and a plurality of ground nodes each in a respective row of substantially parallel rows, wherein each of the plurality of ground nodes is between and neighbors two respective differential signal node pairs arranged in the respective row.

2. A device comprising: a plurality of interconnects arranged in a hexagonal node configuration including a plurality of nodes each neighboring a respective other of the plurality of nodes, wherein, for each node of the plurality of nodes: the node is a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; or a ground node; and the node neighbors six other nodes each selected from a respective group consisting of: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; and a ground node; wherein the plurality of nodes are arranged to form one or more node groups each consisting of a respective seven nodes including: a respective ground node; and a respective six signal nodes each neighboring the ground node, wherein six differential signal node pairs each include a different respective one of the six signal nodes.

3. The device of claim 2 , wherein, the one or more node groups includes a first node group, wherein the six signal nodes of the first node group are positive signal nodes each of a respective differential signal node pair.

4. The device of claim 2 , wherein the one or more node groups includes a first node group, wherein the six signal nodes of the first node group are negative signal nodes each of a respective differential signal node pair.

5. The device of claim 2 , wherein the plurality of nodes are each at substantially a same distance from a respective neighboring node of the plurality of nodes.

6. An apparatus comprising: a microelectronic substrate; and a microelectronic device electrically attached to the microelectronic substrate with a plurality of interconnects extending from a plurality of vias on a land surface of the microelectronic device, the plurality of interconnects arranged in a hexagonal node configuration including a plurality of nodes each neighboring a respective other of the plurality of nodes, the plurality of nodes each at substantially a same distance from a respective one or more neighboring nodes of the plurality of nodes, wherein, for each node of the plurality of nodes: the node is: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; or a ground node; and the node neighbors six other nodes each selected from a respective group consisting of: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; and a ground node; wherein the plurality of nodes includes: differential signal node pairs each arranged along a respective row of substantially parallel rows of the hexagonal node configuration, the differential signal node pairs including a first differential signal node pair and a second differential signal node pair each in arranged along a first row; and a plurality of ground nodes each in a respective row of substantially parallel rows, wherein each of the plurality of ground nodes is between and neighbors two respective differential signal node pairs arranged in the respective row.

7. The apparatus of claim 6 , wherein the plurality of interconnects comprise a plurality of interconnect pins inserted into conductive recesses within a microelectronic socket attached to the microelectronic substrate.

8. The apparatus of claim 6 , wherein the plurality of interconnects comprise a plurality of solder bump interconnects extending between the microelectronic device vias and vias on an attachment surface of the microelectronic substrate.

9. An apparatus comprising: a microelectronic substrate; and a microelectronic device electrically attached to the microelectronic substrate with a plurality of interconnects extending from a plurality of vias on a land surface of the microelectronic device, the plurality of interconnects arranged in a hexagonal node configuration including a plurality of nodes each neighboring a respective other of the plurality of nodes, the plurality of nodes each at substantially a same distance from a respective neighboring node of the plurality of nodes, wherein, for each node of the plurality of nodes: the node is one of: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; and a ground node; and the node neighbors six other nodes each selected from a respective group consisting of: a positive signal node of a respective differential signal node pair; a negative signal node of a respective differential signal node pair; and a ground node; wherein the plurality of nodes are arranged to form one or more node groups each consisting of a respective seven nodes including: a respective ground node; and a respective six signal nodes each neighboring the ground node, wherein six differential signal node pairs each include a different respective one of the six signal nodes.

10. The apparatus of claim 9 , wherein the one or more node groups includes a first node group, wherein the six signal nodes of the first node group are positive signal nodes each of a respective differential signal node pair.

11. The apparatus of claim 9 , wherein the one or more node groups includes a first node group, wherein the six signal nodes of the first node group are negative signal nodes each of a respective differential signal node pair.

12. The apparatus of claim 9 , wherein the plurality of nodes are each at substantially a same distance from a respective neighboring node of the plurality of nodes.

Assignees

• Enriquez Shibayama Raul
• Johansson Jimmy A
• Xiao Kai
• Intel Corp

Inventors

• Enriquez Shibayama Raul
• Johansson Jimmy A
• Xiao Kai

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/267

  Multiple bump connectors having different functions · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title