Semiconductor chip

Patent metadata

Field	Value
Publication number	US-9589914-B2
Application number	US-201414555735-A
Country	US
Kind code	B2
Filing date	Nov 28, 2014
Priority date	Nov 28, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a semiconductor body region comprising a first surface and a second surface opposite the first surface;
a capacitive structure for detecting crack propagation into the semiconductor body region;
wherein the capacitive structure comprises a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; and
wherein the capacitive structure further comprises a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

2. The semiconductor chip of claim 1 ,
wherein the second electrode region at least partially surrounds the semiconductor body region.

3. The semiconductor chip of claim 1 ,
wherein the second electrode region at least substantially extends from the first surface to the second surface.

4. The semiconductor chip of claim 1 , further comprising a first contact pad and a second contact pad,
wherein the first electrode region is electrically coupled to the first contact pad; and wherein the second electrode region is electrically coupled to the second contact pad; and
wherein the first contact pad and the second contact pad are configured to be electrically coupled to a measurement circuit for measuring a characteristic variable of the capacitive structure.

5. The semiconductor chip of claim 4 , further comprising the measurement circuit configured to measure a value of the characteristic variable of the capacitive structure by electrically characterizing the capacitive structure,
wherein the measurement circuit is further configured to determine a crack based on the measured value of the characteristic variable.

6. The semiconductor chip of claim 1 ,
wherein the first electrode region comprises a first material and the second electrode region comprises a second material.

7. The semiconductor chip of claim 6 ,
wherein the first material is a first metal or first metal alloy and the second material is a second metal or second metal alloy.

8. The semiconductor chip of claim 6 ,
wherein the first material is a doped semiconductor of a first conductivity type and the second material is a doped semiconductor of a second conductivity type.

9. The semiconductor chip of claim 6 ,
wherein the first material is a metal or metal alloy and the second material is a doped semiconductor.

10. The semiconductor chip of claim 1 ,
wherein the electrically insulating region comprises a dielectric material.

11. The semiconductor chip of claim 1 ,
wherein the capacitive structure comprises a trench comprising the first electrode region, the second electrode region and the electrically insulating region.

12. The semiconductor chip of claim 11 ,
wherein the first electrode region comprises a first metal or first metal alloy at least partially filling the trench and the second electrode region comprises a second metal or second metal alloy at least partially filling the trench.

13. The semiconductor chip of claim 1 , further comprising a trench,
wherein the first electrode region comprises a first semiconductor region of a first conductivity type comprising a sidewall of the trench, wherein the second electrode region comprises a second semiconductor region of a second conductivity type; and wherein the electrically insulating region comprises a depletion region formed by the first semiconductor region and the second semiconductor region.

14. The semiconductor chip of claim 1 ,
wherein the capacitive structure comprises a first trench comprising the first electrode region; and wherein the capacitive structure comprises a second trench comprising the second electrode region.

15. The semiconductor chip of claim 14 ,
wherein the first electrode region comprises a first metal or first metal alloy at least partially filling the first trench and the second electrode region comprises a second metal or second metal alloy at least partially filling the second trench.

16. The semiconductor chip of claim 1 , further comprising a third electrode region disposed next to the first electrode region, and a further electrically insulating region extending between the third electrode region and the first electrode region.

17. The semiconductor chip of claim 16 ,
wherein the third electrode region and the second electrode region are disposed at opposite sides of the first electrode region.

18. The semiconductor chip of claim 1 ,
wherein the first electrode region and second electrode region form a p-n-junction, wherein the electrically insulating region comprises a depletion region of the p-n-junction.

19. The semiconductor chip of claim 1 ,
wherein a doped portion of the semiconductor body region forms the second electrode region.

20. The semiconductor chip of claim 1 ,
wherein an oxidized portion of the semiconductor body region forms the electrically insulating region.

21. The semiconductor chip of claim 1 ,
wherein the first electrode region forms a sidewall of the semiconductor chip.

22. A semiconductor chip comprising:
a semiconductor body region comprising a first surface and a second surface opposite the first surface;
a capacitive structure for detecting crack propagation into the semiconductor body region;
wherein the capacitive structure comprises a first semiconductor region of a first conductivity type, the first semiconductor region at least partially enclosing a portion of the semiconductor body region and at least substantially extending from the first surface to the second surface; and
wherein the capacitive structure further comprises a second semiconductor region of a second conductivity type opposite the first conductivity type, wherein the second semiconductor region is disposed adjacent to the first semiconductor region, and
wherein the capacitive structure further comprises an electrically insulating region disposed between the first electrode region and the second electrode region, the electrically insulating region comprising a depletion region formed from the first semiconductor region of a first conductivity type and the second semiconductor region of a second conductivity type.

23. The semiconductor chip of claim 22 ,
wherein the second semiconductor region at least partially encloses the semiconductor body region, and wherein the second semiconductor region at least substantially extends from the first surface to the second surface.

24. A semiconductor chip comprising:
a semiconductor body region comprising a first surface and a second surface opposite the first surface;
a capacitive structure for detecting crack propagation into the semiconductor body region;
wherein the capacitive structure comprises a first electrode region comprising a first metal or first metal alloy and a second electrode region comprising a second metal or second metal alloy disposed next to the first electrode region, the first and second electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; and
wherein the capacitive structure further comprises an electrically insulating region disposed between the first electrode region and the second electrode region, wherein the capacitive structure comprises a trench comprising the firs

Assignees

• Infineon Technologies Ag

Inventors

• Gietler Herbert
• Pressl Robert

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title