Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9589842-B2
Application number	US-201614993054-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Jan 30, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
providing a plurality of semiconductor chips on a support substrate, the semiconductor chips spaced apart from each other on the support substrate;
forming a protection layer covering top surfaces of the plurality of semiconductor chips;
forming a molding layer covering the support substrate and the protection layer; and
etching the molding layer formed on the protection layer to expose the protection layer,
wherein a thickness of the protection layer is reduced after etching the molding layer formed on the protection layer.

2. The method of claim 1 , wherein first portions of a bottom surface of the protection layer are in contact with the top surfaces of the plurality of semiconductor chips.

3. The method of claim 2 , wherein second portions of the bottom surface of the protection layer are not in contact with the top surfaces of the plurality of semiconductor chips and have a thickness greater than that of the first portions of the protection layer with the bottom surface in contact the top surfaces of the plurality of the semiconductor chips.

4. The method of claim 2 , wherein second portions of the bottom surface of the protection layer are not in contact with the top surfaces of the plurality of semiconductor chips and are spaced apart from a top surface of the support substrate.

5. The method of claim 1 , wherein forming the protection layer comprises:
forming a plurality of spaces between the semiconductor chips, wherein the spaces are defined by sidewalls of adjacent semiconductor chips, a top surface of the support substrate and a bottom surface of the protection layer.

6. The method of claim 5 , wherein forming the molding layer comprises:
forming a molding member and a sacrificial member, wherein the spaces are filled by the molding member, and the sacrificial member is formed on the protection layer.

7. The method of claim 6 , wherein etching the molding layer comprises:
substantially completely removing the sacrificial member while leaving the molding member.

8. The method of claim 6 , wherein etching the molding layer comprises:
substantially completely removing the sacrificial member; and
etching an upper portion of the protection layer.

9. The method of claim 1 , wherein the protection layer comprises a tape type and is adhered to the top surfaces of the plurality of semiconductor chips.

10. The method of claim 1 , further comprising:
separating the support substrate from the plurality of semiconductor chips;
forming an insulating layer on bottom surfaces of the plurality of semiconductor chips;
forming a plurality of interconnections in the insulating layer, each interconnection electrically connected to a corresponding one of the plurality of semiconductor chips;
forming a plurality of terminal pads on corresponding ones of the plurality of interconnections;
forming a plurality of external terminals on corresponding ones of the plurality of terminal pads; and
cutting the protection layer, the molding layer, and the insulating layer to separate each semiconductor chip package including a semiconductor chip by a singulation process.

11. A method of fabricating semiconductor packages, the method comprising:
providing semiconductor chips on a support substrate, the semiconductor chips laterally spaced apart from each other, and each of the semiconductor chips including a chip pad disposed on a bottom surface;
forming a protection layer covering top surfaces of the semiconductor chips;
forming a molding layer covering the support substrate and the protection layer;
etching the molding layer formed on the protection layer to expose the protection layer;
separating the support substrate from the semiconductor chips;
forming an insulating layer on bottom surfaces of the semiconductor chips;
forming an interconnection being in contact with the chip pad in the insulating layer;
forming a terminal pad on the interconnection; and
forming an external terminal on the terminal pad,
wherein a thickness of the protection layer is reduced after etching the molding layer formed on the protection layer.

12. The method of claim 11 , wherein the protection layer comprises a tape type and is adhered to the top surfaces of the semiconductor chips.

13. The method of claim 11 , wherein first portions of the protection layer are in contact with the top surfaces of the semiconductor chips.

14. The method of claim 13 , wherein second portions of the protection layer are not in contact with the top surfaces of the semiconductor chips and have a thickness greater than that of the first portions of the protection layer with the bottom surface in contact with the top surfaces of the semiconductor chips.

15. The method of claim 11 , wherein forming the protection layer comprises:
forming a space between the semiconductor chips, wherein the space is defined by sidewalls of adjacent semiconductor chips, a top surface of the support substrate and a bottom surface of the protection layer.

16. A method of fabricating semiconductor packages, the method comprising:
providing a plurality of semiconductor chips on a support substrate, the semiconductor chips being spaced apart from each other on the support substrate, and each semiconductor chip comprising a top surface;
forming a protection layer covering the top surfaces of the plurality of semiconductor chips and covering a plurality of spaces between two adjacent semiconductor chips, the protection layer comprising a top surface;
forming a molding layer covering the top surface of the protection layer, and filling the plurality of spaces; and
etching the molding layer formed on the protection layer to expose the protection layer,
wherein a thickness of the protection layer is reduced after etching the molding layer formed on the protection layer.

17. The method of claim 16 , wherein each of the plurality of spaces is defined by sidewalls of two adjacent semiconductor chips, a bottom surface of the protection layer and a top surface of the support substrate.

18. The method of claim 17 , wherein the protection layer comprises a tape type and wherein forming a protection layer includes disposing the protection layer on the top surfaces of the plurality of semiconductor chips and covering the plurality of spaces.

19. The method of claim 17 , wherein forming the molding layer comprises forming a molding member and a sacrificial member, wherein the spaces are filled by the molding member, wherein the sacrificial member is formed on the protection layer, and wherein the molding layer is formed by a capillary underfill method or a molded underfill method.

20. The method of claim 16 , further comprising:
providing a plurality of connecting elements on a same side of the support substrate as the plurality of semiconductor chips, wherein each of the connecting elements is spaced apart and adjacent to one of the plurality of semiconductor chips; wherein the protection layer is formed to cover the top surfaces of the plurality of semiconductor chips and top surfaces of the connecting elements.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Inho
• Kim Donghan
• Kim Jae Choon
• Song Jikho
• Umemoto Mitsuo

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title