Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9589840-B2
Application number	US-201414274289-A
Country	US
Kind code	B2
Filing date	May 9, 2014
Priority date	May 9, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.

First claim

What is claimed is:

1. A semiconductor element, comprising:
a main body defining at least one receiving space penetrating through the main body;
a plurality of conductive vias penetrating through the main body; and
at least one filler located in the receiving space, wherein a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias, and the filler is located between at least two conductive vias;
wherein the at least one receiving space has at least one first opening on a surface of the main body, and a length of the first opening is greater than a pitch between two conductive vias,
wherein the filler divides the main body into a plurality of individual blocks,
wherein the plurality of individual blocks are fully isolated from one another by the filler.

2. The semiconductor element according to claim 1 , wherein the main body defines a plurality of holes penetrating through the main body, each of the conductive vias includes a liner and a conductive metal, the liner is located on a side wall of a respective hole and defines a central hole, and the central hole is filled with the conductive metal.

3. The semiconductor element according to claim 1 , wherein a ratio of a total area of all the at least one first opening to a total surface area of the surface of the main body is 5% to 50%.

4. The semiconductor element according to claim 1 , wherein the at least one first opening forms at least one segment on the surface of the main body, and the at least one segment is arranged in a rectangular shape, an L shape, a cross shape, or a grid shape.

5. The semiconductor element according to claim 1 , wherein a material of the main body is a semiconductor material, and a material of the filler is a polymer or a metal.

6. The semiconductor element according to claim 1 , further comprising at least one insulating layer, located between the filler and a side wall of the receiving space.

7. The semiconductor element according to claim 1 , wherein the main body further comprises a plurality of electrical elements.

8. A semiconductor package, comprising:
a substrate;
a semiconductor element located above the substrate, the semiconductor element comprising:
a main body defining at least one receiving space penetrating through the main body;
a plurality of conductive vias penetrating through the main body; and
at least one filler located in the receiving space, wherein a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias, and the filler is located between at least two conductive vias;
wherein the at least one receiving space has at least one first opening on a surface of the main body, and a length of the first opening is greater than a pitch between two conductive vias;
wherein the filler divides the main body into a plurality of individual blocks;
wherein the plurality of individual blocks are fully isolated from one another by the filler;

a plurality of solder balls connecting the substrate and the semiconductor element, and electrically connected to the conductive vias; and
at least one chip including at least one bump, disposed above the semiconductor element.

9. The semiconductor package according to claim 8 , wherein a ratio of a total area of all the at least one first opening to a total surface area of the surface of the main body is 5% to 50%.

10. The semiconductor package according to claim 8 , further comprising an underfill covering the at least one bump.

11. The semiconductor package according to claim 8 , further comprising a molding compound covering an upper surface of the at least one chip.

12. The semiconductor package according to claim 8 , wherein the main body further comprises a plurality of electrical elements.

13. The semiconductor package according to claim 8 , wherein the filler fully surrounds a lateral periphery of at least one of the plurality of individual blocks.

14. A semiconductor element, comprising:
a semiconductor body, the semiconductor body defining a plurality of openings extending from a top surface of the semiconductor body to a bottom surface of the semiconductor body, the plurality of openings including at least two first openings and at least one second opening positioned between the at least two first openings;
an upper redistribution layer disposed at the top surface of the semiconductor body;
a lower redistribution layer disposed at the bottom surface of the semiconductor body;
at least two conductive vias respectively disposed in the at least two first openings, the at least two conductive vias electrically connected to the upper redistribution layer and the lower redistribution layer; and
at least one filler respectively disposed in the at least one second opening, wherein a coefficient of thermal expansion (CTE) of the at least one filler is greater than a CTE of the semiconductor body, and the CTE of the at least one filler is different from a CTE of the at least two conductive vias, and the filler is located between the at least two conductive vias,
wherein a length of the at least one second opening is greater than a pitch between two conductive vias,
wherein the filler divides the semiconductor body into a plurality of individual blocks;
wherein the plurality of individual blocks are fully isolated from one another by the filler.

15. The semiconductor element of claim 14 , wherein the CTE of the least one filler is less than the CTE of the at least two conductive vias.

16. The semiconductor element of claim 14 , wherein the at least one second opening is a plurality of second openings and the at least one filler is a plurality of fillers respectively disposed in the plurality of second openings, wherein the plurality of fillers divide the semiconductor body into the plurality of individual blocks.

17. The semiconductor element of claim 14 , wherein the at least one filler is a conductive material, and the at least one filler is electrically isolated from the upper redistribution layer and the lower redistribution layer.

18. The semiconductor element of claim 14 , wherein the filler fully surrounds a lateral periphery of at least one of the plurality of individual blocks.

Assignees

• Advanced Semiconductor Eng

Inventors

• Kao Chin-Li
• Lee Chang-Chi
• Lai Yi-Shao

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title