Gate electrode of field effect transistor

Patent metadata

Field	Value
Publication number	US-9589803-B2
Application number	US-201213572494-A
Country	US
Kind code	B2
Filing date	Aug 10, 2012
Priority date	Aug 10, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

First claim

What is claimed is:

1. A field effect transistor comprising:
a substrate;
a gate electrode over the substrate comprising a first top surface and a sidewall, wherein the gate electrode has a first thickness;
a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode;
a spacer on the sidewall distributed between the gate electrode and a portion of the S/D region;
a gate dielectric layer between the substrate and the gate electrode; and
a contact etch stop layer (CESL) adjacent to the spacer, wherein, the CESL over the S/D region has a second thickness, and a ratio of the first thickness to the second thickness ranges from about 1.1 to about 1.5, wherein an entire top surface of the CESL over the S/D region and over an isolation region adjoining the field effect transistor is substantially co-planar with the first top surface of the gate electrode.

2. The field effect transistor of claim 1 , wherein an aspect ratio of the gate electrode is from about 0.8 to about 1.2.

3. The field effect transistor of claim 1 , wherein the portion of the S/D region is above the substrate.

4. The field effect transistor of claim 1 , wherein the gate electrode comprises poly-silicon, a P-work-function metal or an N-work-function metal.

5. The field effect transistor of claim 1 , wherein the gate electrode comprises a P-work-function metal, the P-work-function metal comprises TiN, WN, TaN, and Ru.

6. The field effect transistor of claim 1 , wherein the gate electrode comprises an N-work-function metal, the N-work-function metal comprises Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.

7. The field effect transistor of claim 1 , wherein the CESL comprises silicon nitride, silicon oxy-nitride, silicon carbide, or carbon-doped silicon nitride.

8. The field effect transistor of claim 1 , wherein the source/drain (S/D) region comprises a strained material, wherein a lattice constant of the strained material is different from a lattice constant of the substrate.

9. The field effect transistor of claim 8 , wherein the strained material comprises SiGe, SiGeB, SiP or SiC.

10. The field effect transistor of claim 1 , wherein the spacer comprises silicon nitride, silicon oxy-nitride, silicon carbide, or carbon-doped silicon nitride.

11. The field effect transistor of claim 1 , wherein the field effect transistor is a Fin field effect transistor.

12. A field effect transistor comprising:
a substrate;
a gate electrode over the substrate comprising a first top surface and a sidewall, wherein an aspect ratio of the gate electrode ranges from about 0.8 to about 1.2;
a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode;
a gate dielectric layer over the substrate and under the gate electrode;
a contact etch stop layer (CESL) surrounding the sidewall of the gate electrode and the sidewall of the gate dielectric, and a ratio of a height of the gate electrode to a distance from a top surface of the S/D region to the second top surface ranging from about 0.5 to about 0.9, wherein an entire top surface of the CESL over the S/D region and over an isolation region adjoining the field effect transistor is substantially planar with a top surface of the gate electrode, wherein the isolation region is in the substrate, and wherein the CESL contacts a sidewall of the isolation region below a top surface of the substrate.

13. The field effect transistor of claim 12 , wherein the gate dielectric layer comprises a high-k dielectric material.

14. The field effect transistor of claim 13 , further comprising an interfacial layer between the gate dielectric layer and the substrate.

15. The field effect transistor of claim 12 , wherein the S/D region has tapered sidewalls.

16. The field effect transistor of claim 1 , wherein the CESL extends over a top surface of the isolation region, and the CESL contacts a sidewall of the isolation region below a top surface of the substrate.

17. The field effect transistor of claim 1 , wherein a portion of the S/D region above the substrate is free of the spacer.

18. The field effect transistor of claim 1 , wherein the gate dielectric layer comprises a high-k dielectric material.

19. The field effect transistor of claim 12 , wherein the CESL is against a top surface of the isolation region.

20. The field effect transistor of claim 18 , wherein the S/D region is entirely below a top surface of the substrate.

Assignees

• Chen Neng-Kuo
• Wann Clement Hsingjen
• Lin Yi-An
• Chang Chun-Wei
• Sun Sey-Ping
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Neng-Kuo
• Wann Clement Hsingjen
• Lin Yi-An
• Chang Chun-Wei
• Sun Sey-Ping

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/266

  by vapour etching only · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title