Gate drive circuit and drive method for the same

Patent metadata

Field	Value
Publication number	US-9589667-B2
Application number	US-201514730164-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Dec 31, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A gate drive circuit is disclosed. The drive circuit includes M cascaded shift registers, where M is a natural number, and a clock controller configured to generate two reverse-phase clock signals. The drive circuit also includes a high level controller configured to generate a high level signal, and a low level controller configured to generate a low level signal, where one of the high level controller and the low level controller is configured to generate an initial pulse signal during an initial stage. The drive circuit also includes a start unit cascaded with the M shift registers, where the start unit is configured to provide a start signal to the shift registers.

First claim

What is claimed is:

1. A gate drive circuit, comprising:
M cascaded shift registers, wherein M is a natural number;
a clock controller, configured to generate two reverse-phase clock signals;
a high level controller configured to generate a high level signal;
a low level controller configured to generate a low level signal,
wherein one of the high level controller and the low level controller is configured to generate an initial pulse signal during an initial stage; and
a start unit cascaded with the M shift registers, wherein the start unit is configured to provide a start signal to the shift registers.

2. The gate drive circuit according to claim 1 , wherein:
the start unit comprises a first input terminal and a second input terminal;
one of:
the first input terminal is connected to the high level controller and is configured to receive the high level signal and the initial pulse signal, wherein the initial pulse signal is a low level pulse signal, and the second input terminal is connected to the low level controller and is configured to receive the low level signal, and
the first input terminal is connected to the low level controller and is configured to receive the low level signal and the initial pulse signal, wherein the initial pulse signal is a high level pulse signal, and the second input terminal is connected to the high level controller and is configured to receive the high level signal;

the start unit further comprises:
a third input terminal,
a first clock terminal and a second clock terminal, wherein the first clock terminal is connected to the clock controller and is configured to receive one of the two reverse-phase clock signals, and wherein the second clock terminal is connected to the clock controller and is configured to receive the other one of the two reverse-phase clock signals, and
a first output terminal;

the shift register comprises:
an a-th input terminal connected to the high level controller or the low level controller to which the first input terminal is connected,
a b-th input terminal connected to the high level controller or the low level controller to which the second input terminal is connected,
a c-th input terminal,
a d-th input terminal, wherein the d-th input terminal of a first stage shift register is connected to the first output terminal to input the start signal,
an a-th clock terminal and a b-th clock terminal, wherein the a-th clock terminal is connected to the clock controller and is configured to receive one of the two reverse-phase clock signals, and wherein the b-th clock terminal is connected to the clock controller and is configured to receive the other one of the two reverse-phase clock signals, and
an a-th output terminal, wherein the a-th output terminal of the first stage shift register is connected to the third input terminal, wherein the a-th output terminal of each of the shift registers other than the first stage shift register is connected to the c-th input terminal of a former stage shift register, and wherein the a-th output terminal of each of the shift registers is connected to the d-th input terminal of a latter stage shift register.

3. The gate drive circuit according to claim 2 , wherein the start unit comprises:
a first transistor, wherein a gate of the first transistor is connected to the first input terminal, and wherein a drain of the first transistor is connected to the second input terminal;
a second transistor, wherein a gate of the second transistor is connected to a source of the first transistor, and wherein a source of the second transistor is connected to the first clock terminal; and
a first capacitor connected between the source of the first transistor and the first clock terminal.

4. The gate drive circuit according to claim 3 , wherein:
the start unit comprises:
a third transistor, wherein a gate of the third transistor is connected to the third input terminal, wherein a source of the third transistor is connected to the drain of the second transistor, and wherein a drain of the third transistor is connected to the second input terminal,
a fourth transistor, wherein a gate of the fourth transistor is connected to the drain of the second transistor, wherein a source of the fourth transistor is connected to the second clock terminal, and wherein a drain of the fourth transistor is connected to the first output terminal,
a fifth transistor, wherein a gate of the fifth transistor is connected to the first clock terminal, wherein a source of the fifth transistor is connected to the first output terminal, and wherein a drain of the fifth transistor is connected to the second input terminal, and
a second capacitor connected between the drain of the second transistor and the first output terminal;

the shift register comprises:
a b-th transistor, wherein a gate of the b-th transistor is connected to the d-th input terminal, and wherein a source of the b-th transistor is connected to the a-th input terminal,
a c-th transistor, wherein a gate of the c-th transistor is connected to the c-th input terminal, wherein a source of the c-th transistor is connected to a drain of the b-th transistor, and wherein a drain of the c-th transistor is connected to the b-th input terminal,
a d-th transistor, wherein a gate of the d-th transistor is connected to the drain of the b-th transistor, wherein a source of the d-th transistor is connected to the b-th clock terminal, and wherein a drain of the d-th transistor is connected to the a-th output terminal;
an e-th transistor, wherein a gate of the e-th transistor is connected to the a-th clock terminal, wherein a source of the e-th transistor is connected to the a-th output terminal, and wherein a drain of the e-th transistor is connected to the b-th input terminal, and
a b-th capacitor connected between the drain of the b-th transistor and the a-th output terminal.

5. The gate drive circuit according to claim 4 , wherein the start unit further comprises a sixth transistor, wherein a gate and a source of the sixth transistor are connected, wherein the gate of the sixth transistor is connected to the first clock terminal, and wherein a drain of the sixth transistor is connected to the gate of the fifth transistor.

6. The gate drive circuit according to claim 4 , wherein the shift register further comprises an f-th transistor, wherein a gate and a source of the f-th transistor are connected, wherein the gate of the f-th transistor is connected to the a-th clock terminal, and wherein a drain of the f-th transistor is connected to the gate of the e-th transistor.

7. The gate drive circuit according to claim 4 , wherein the start unit further comprises a seventh transistor, wherein a gate of the seventh transistor is connected to the drain of the second transistor, wherein a source of the seventh transistor is connected to the gate of the fifth transistor, and wherein a drain of the seventh transistor is connected to the second input terminal.

8. The gate drive circuit according to claim 4 , wherein the shift register further comprises a g-th transistor, wherein a gate of the g-th transistor is connected to the drain of the b-th transistor, wherein a source of the g-th transistor is connected to the gate of the e-th transistor, and wherein a drain of the g-th transistor is connected to the b-th input terminal.

9. The gate drive circuit according to claim 4 , wherein the start unit further comprises an eighth transistor, wherein a gate of the eighth transistor is connected to the gate of the fifth transistor, wherein a source of the eighth transistor is connected to the drain of the second transistor, and wherein a drain of the eighth transistor is connected to the second input terminal.

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Cao Zhaokeng
• Wang Tinghai
• Qin Dandan

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title