Block refresh to adapt to new die trim settings

Patent metadata

Field	Value
Publication number	US-9589645-B2
Application number	US-201414507245-A
Country	US
Kind code	B2
Filing date	Oct 6, 2014
Priority date	Oct 6, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.

First claim

What is claimed is:

1. A system for adapting to trim set advancement, wherein trim set advancement is a change in trim sets over time, the system comprising:
a semiconductor memory comprising a cell having a first charge level, the cell raised to the first charge level representing a value when the cell was programmed to the value with a first trim set;
a charge circuit configured to add a charge to the cell; and
a controller configured to direct the charge circuit to raise the first charge level of the cell to a second charge level that corresponds to the cell programmed to the value with a second trim set, the second trim set different than the first trim set.

2. The system of claim 1 wherein the controller is further configured to read a value from the cell with the second trim set after the first charge level is raised to the second charge level and to verify the value read matches the value represented by the first charge level of the cell.

3. The system of claim 1 further comprising a program circuit that includes the charge circuit, wherein the controller is configured to read the value from the cell with the first trim set and to load the value to the program circuit, wherein the charge circuit raises the first charge level of the cell to the second charge level based on the value loaded to the program circuit.

4. The system of claim 1 , wherein the charge circuit is configured to raise the first charge level of the cell to the second charge level based on execution of a fine program operation of a foggy fine programming algorithm without execution of any other stages of the foggy fine programming algorithm.

5. The system of claim 1 wherein the controller is further configured to change a current trim set from the first trim set to the second trim set, wherein the controller is configured to direct the charge circuit to raise the first charge level of the cell to the second charge level in response to the change of the current trim set.

6. The system of claim 1 wherein the controller is configured to direct the charge circuit to raise the first charge level of the cell to the second charge level in response to detection of an error in data read from the cell.

7. The system of claim 1 wherein the semiconductor memory includes a three dimensional memory array.

8. A method to adapt to a change in trim sets over time, the method comprising:
programming a cell of a semiconductor memory with a first trim set, the cell having a charge level raised to a first charge level by the programming; and
reprogramming the cell by raising the first charge level to a second charge level, the second charge level corresponding to the cell programmed with a second trim set that is different than the first trim set.

9. The method of claim 8 wherein raising the first charge level to the second charge level is performed as part of a block refresh.

10. The method of claim 8 wherein raising the first charge level to the second charge level is in response to a read scrub.

11. The method of claim 8 wherein raising the first charge level to the second charge level is in response to a trim set advancement.

12. The method of claim 8 further comprising reprogramming a page, which was programmed with the first trim set, by performing a fine program operation on the page without erasing the page.

13. The method of claim 8 further comprising reading data from the cell programmed with the first trim set, wherein raising the first charge level to the second charge level comprises writing the data to the cell with parameters from the second trim set.

14. A memory device comprising:
a semiconductor memory comprising a plurality of word lines, the word lines including a word line programmed with a first program setting, the programmed word line charged to a first charge level representative of a stored value at the first program setting;
a controller configured to read the stored value from the programmed word line; and
a charge circuit configured to add a charge to any of the word lines selected for programming,
wherein the controller is further configured to direct the charge circuit to change the first charge level of the programmed word line to a second charge level, the second charge level representative of the stored value programmed with a second program setting, the second program setting different than the first program setting.

15. The memory device of claim 14 , wherein the controller is further configured to verify a value read from the programmed word line with the second program setting after the first charge level is changed to the second charge level.

16. The memory device of claim 14 , wherein the controller is further configured to cache the stored value read by the read module, wherein the charge circuit changes the first charge level to the second charge level based on the cached stored value.

17. The memory device of claim 14 further comprising a program circuit configured to program any of the word lines, wherein the charge circuit is included in the program circuit, and wherein the charge circuit is configured to changes the first charge level of the programmed word line to the second charge level based on execution of a fine program operation of a foggy fine programming algorithm without other stages of the foggy fine programming algorithm.

18. The memory device of claim 14 further comprising a test circuit that includes the charge circuit, wherein the test circuit is configured to adjust any charge level in any of the word lines to a target charge level.

19. The memory device of claim 14 , wherein the controller is configured to direct the charge circuit to change a respective charge level of each word line in a block to a corresponding second charge level, the corresponding second charge level consistent with each word line in the block having been programmed with the second program setting.

20. The memory device of claim 14 , wherein the adaptation module is configured to direct the charge circuit to change the first charge level of the programmed word line to the second charge level as part of a block refresh in which charge lost to charge decay over time is restored to the programmed word line.

21. A memory device comprising:
a semiconductor memory comprising a plurality of word lines, the word lines including a word line programmed with a first program setting, the programmed word line charged to a first charge level representative of a stored value at the first program setting;
a means for reading the stored value from the programmed word line; and
a means for raising the first charge level of the programmed word line to a second charge level, the second charge level representative of the stored value programmed with a second program setting, the second program setting different than the first program setting.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Dusija Gautam
• Avila Chris
• Hsu Jonathan
• Darragh Neil
• Lei Bo

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title