Energy efficient three-terminal voltage controlled memory cell

Patent metadata

Field	Value
Publication number	US-9589616-B2
Application number	US-201514927500-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Nov 2, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Memory cell, method for operating the memory cell and method for fabricating the memory cell are disclosed. The memory cell includes at least three terminals, a first magnetic tunnel junction (MTJ) structure and a second MTJ structure. The first MTJ is coupled between a first terminal (FT) and a third terminal. A portion of the first MTJ is configured to include a first barrier layer disposed between a first fixed layer and a free layer (FL). A magnetization direction of the FL is used to store data, the magnetization direction being controlled by an electric field. The second MTJ is coupled between the FT and a second terminal, where a portion of the second MTJ is configured to include a second barrier layer disposed between a second fixed layer and the FL, where a tunnel magnetoresistance of the second barrier layer is used to read the data.

First claim

What is claimed is:

1. A memory cell comprising:
at least three terminals including first, second, and third terminals;
a first magnetic tunnel junction (MTJ) structure coupled between the first terminal and the third terminal, wherein a portion of the first MTJ structure is configured to include a first barrier layer disposed between a first fixed layer and a free layer, wherein magnetization direction of the free layer is used to store data, the magnetization direction being controlled by an electric field;
a second MTJ structure coupled between the first terminal and the second terminal, wherein a portion of the second MTJ structure is configured to include a second barrier layer disposed between a second fixed layer and the free layer, wherein a tunnel magnetoresistance (TMR) of the second barrier layer is used to read the data, wherein the first terminal comprises a first conductive plug which covers a first portion of the second barrier layer;
a conductive top lead layer coupled to the second terminal, the conductive top lead layer being disposed to cover the second fixed layer, wherein the second fixed layer covers a second portion of the second barrier layer; and
a spacer configured to insulate the first conductive plug from the conductive top lead layer and the second fixed layer, wherein the spacer covers a center portion of the second barrier layer.

2. The memory cell of claim 1 , wherein a read electrical path enables an electrical signal to flow through the second MTJ structure to perform a read operation, wherein the read electrical path is configured to include:
the first terminal;
the second barrier layer;
the free layer;
the second fixed layer;
the conductive top lead layer; and
the second terminal.

3. The memory cell of claim 2 , wherein the read electrical path is configured to bypass the first barrier layer.

4. The memory cell of claim 2 , wherein a direction of the read electrical path is configured to be in plane with the free layer.

5. The memory cell of claim 1 , wherein the first MTJ structure further comprises a conductive bottom lead layer coupled to the third terminal, wherein the first fixed layer covers the conductive bottom lead layer.

6. The memory cell of claim 5 , wherein a write electrical path enables an electrical signal to flow through the first MTJ structure to perform a write operation, wherein the write electrical path is configured to include:
the first terminal;
the second barrier layer;
the free layer;
the first barrier layer;
the first fixed layer;
the conductive bottom lead layer; and
the third terminal.

7. The memory cell of claim 6 , wherein a direction of the write electrical path is configured to be perpendicular to the free layer.

8. The memory cell of claim 6 , wherein the write electrical path is configured to bypass the second terminal and the second fixed layer.

9. The memory cell of claim 6 , wherein a voltage applied between the first terminal and the third terminal controls the magnetization direction to perform the write operation of the data, wherein a value of the data stored in the free layer is determined by the magnetization direction.

10. The memory cell of claim 6 , wherein time to perform the write operation is at most equal to about 1 nanoseconds.

11. The memory cell of claim 1 , wherein a Tantalum (Ta) based seed layer is inserted between the first fixed layer and first barrier layer to increase crystallization of the first barrier layer.

12. The memory cell of claim 11 , wherein the Tantalum (Ta) based seed layer provides a self-biased static field in the first fixed layer to trigger spin precession in the free layer.

13. The memory cell of claim 1 , wherein the magnetization direction is controlled by switching the electric field, wherein the switching causes a change in the magnetization direction from being perpendicular to plane direction of the free layer to being in plane with the free layer in dependence of the electric field.

14. The memory cell of claim 13 , wherein the switching changes a perpendicular magnetic anisotropy (PMA) property of the free layer to cause a voltage induced precessional dynamic switching of the magnetization direction.

15. The memory cell of claim 1 , wherein a ratio of a thickness of the first barrier layer to a thickness of the second barrier layer is between 2:1 and 5:1.

16. The memory cell of claim 1 , wherein the first barrier layer is configured to include a Magnesium Oxide (MgO) based dielectric material, wherein the second barrier layer is configured to include another oxide based dielectric material that is different than the MgO based dielectric material.

17. A method for operating a memory cell, the method comprising:
providing the memory cell, wherein the memory cell includes
at least three terminals including first, second, and third terminals,
a first magnetic tunnel junction (MTJ) structure coupled between the first terminal and the third terminal, wherein a portion of the first MTJ structure is configured to include a first barrier layer disposed between a first fixed layer and a free layer, and
a second MTJ structure coupled between the first terminal and the second terminal, wherein a portion of the second MTJ structure is configured to include a second barrier layer disposed between a second fixed layer and the free layer;

receiving a request to write data;
applying an electric field across the first terminal and the third terminal to control magnetization direction of the free layer; and
writing the data to the free layer, wherein the magnetization direction of the free layer is used to store the data, and wherein a tunnel magnetoresistance (TMR) of the second barrier layer is used to read the data.

18. A method for fabricating a memory cell, the method comprising:
forming a magnetic tunnel junction (MTJ) stack, the MTJ stack including
a conductive bottom lead layer coupled to a third terminal,
a first fixed layer formed to cover the conductive bottom lead layer,
a first barrier layer formed to cover the first fixed layer,
a free layer formed to cover the first barrier layer,
a second barrier layer formed to cover the free layer,
a second fixed layer formed to cover the second barrier layer, and
a conductive top lead layer formed to cover the second fixed layer;

etching end portions of the MTJ stack to form a first intermediate MTJ structure;
forming a first protective layer to protect the first intermediate MTJ structure;
backfilling the end portions of the first intermediate MTJ structure;
planarizing the first MTJ stack to form a second intermediate MTJ structure;
etching a side portion of the second intermediate MTJ structure to form a third intermediate MTJ structure, wherein the etching exposes a portion of the second barrier layer;
forming a second protective layer to protect the exposed portion of the third intermediate MTJ structure;
backfilling the exposed portion of the third intermediate MTJ structure to form a fourth intermediate MTJ structure;
etching a first portion of the fourth intermediate MTJ structure to expose a portion of the second barrier layer and etching a second portion of the fourth intermediate MTJ structure to expose a portion of the conductive top lead layer to form a fifth intermediate MTJ structure; and
filling the first portion and the second portion of the fifth intermediate MTJ structure with conductive material to form the first terminal and the second terminal respectively.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Meng Hao
• Poh Yong Wee Francis
• Chan Tze Ho Simon

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/14

  using thin-film elements · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H01L43/08

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title