Digitally trimmable integrated resistors including resistive memory elements

Patent metadata

Field	Value
Publication number	US-9589615-B2
Application number	US-201514750670-A
Country	US
Kind code	B2
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A circuit comprising:
one or more circuit elements to process an analog signal on a signal path; and
a resistor coupled with the signal path to pass the analog signal along the signal path, the resistor including a plurality of resistor cells coupled to one another in a series-parallel combination, wherein respective resistances of individual resistor cells of the plurality of resistor cells are adjustable to adjust an overall resistance of the resistor, and wherein individual resistor cells of the plurality of resistor cells include:
a resistive memory element coupled on the signal path and including first and second terminals;
a source line to receive a source line signal;
a bit line to receive a bit line signal;
a first transistor coupled between the source line and the first terminal of the resistive memory element; and
a second transistor coupled between the bit line and the second terminal of the resistive memory element, wherein the signal path does not pass through the first and second transistors.

2. The circuit of claim 1 , wherein the respective resistances of individual resistor cells of the plurality of resistor cells are digitally adjustable.

3. The circuit of claim 1 , wherein the resistive memory element includes a magnetic tunnel junction (MTJ) element.

4. The circuit of claim 3 , wherein the MTJ element includes a free layer coupled to the second terminal and a pinned layer coupled to the first terminal, and wherein the individual resistor cells further include:
a word line to receive a word line signal, the word line coupled to a (late terminal of the first transistor and a gate terminal of the second transistor.

5. The circuit of claim 1 , wherein the resistive memory element includes a conducting bridge random access memory (CBRAM) resistive element, a phase change random access memory (PCRAM) resistive element, or a resistive random access memory (RRAM) resistive element.

6. The circuit of claim 1 , wherein the resistor is disposed in one or more upper metal layers of the circuit that are above an active substrate region of the circuit.

7. The circuit of claim 1 , wherein the circuit is a digital-to-analog conversion (DAC) circuit or an analog-to-digital conversion (ADC) circuit.

8. The circuit of claim 1 , wherein the circuit is a biasing circuit, an input/output circuit, or a radio frequency circuit.

9. A circuit comprising:
a signal path; and
a resistor coupled with the signal path to pass a signal along the signal path, the resistor including:
a magnetic tunnel junction (MTJ) element coupled on the signal path, the MTJ including a free layer and a pinned layer;
a source line to receive a source line signal;
a bit line to receive a bit line signal;
a first transistor coupled between the source line and the pinned layer of the MTJ element; and

a second transistor coupled between the bit line and the free layer of the MTJ element wherein the signal path does not pass through the first and second transistors.

10. The circuit of claim 9 , further comprising a word line to receive a word line signal, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the word line to receive the word line signal.

11. The circuit of claim 10 , wherein, when the word line signal has a first value, the MTJ element is switchable between a first resistance and a second resistance based on a value of the source line signal and a value of the bit line signal.

12. The circuit of claim 10 , wherein the resistor is a first resistor, the MTJ element is a first MTJ element, the word line is a first word line, and the word line signal is a first word line signal, and wherein the circuit further includes a second resistor that includes:
a second word line to receive a second word line signal;
a third transistor coupled between the source line and a pinned layer of a second MTJ element, a gate terminal of the third transistor coupled to the second word line; and
a fourth transistor coupled between the bit line and a free layer of the second MTJ element, a gate terminal of the fourth transistor coupled to the second word line.

13. The circuit of claim 9 , wherein the MTJ element, first transistor, and second transistor are included in a first resistor cell of the resistor, and wherein the resistor includes a plurality of resistor cells, including the first resistor cell, coupled in a series-parallel combination.

14. The circuit of claim 9 , wherein the signal is an analog signal.

15. The circuit of claim 9 , wherein the circuit is a radio frequency circuit.

16. The circuit of claim 9 , wherein the circuit is a digital-to-analog conversion (DAC) circuit, an analog-to-digital conversion (ADC) circuit, a biasing circuit, or an input/output circuit.

17. The circuit of claim 9 , further comprising a calibration circuit to control the bit line signal, the source line signal, and a word line signal to adjust a resistance of the resistor.

18. The circuit of claim 9 , further comprising a passive resistor coupled in series with the MTJ element on the signal path, wherein a resistance of the passive resistor is greater than a maximum resistance of the MTJ element.

19. A system comprising:
a memory;
a processor coupled to the memory; and
circuitry coupled to the processor and separate from the memory, the circuitry including a series-parallel combination of magnetic tunnel junction (MTJ) elements to form a resistor coupled with a signal path to pass an analog signal, wherein the MTJ elements are included in respective resistor cells of the resistor and include a first MTJ element included in a first resistor cell of the resistor, and wherein the first resistor cell further includes:
a source line to receive a source line signal;
a bit line to receive a bit line signal;
a word line to receive a word line signal;
a first transistor coupled between the source line and a pinned layer of the first MTJ element, a gate terminal of the first transistor coupled to the word line; and
a second transistor coupled between the bit line and a free layer of the first MTJ element, a gate terminal of the second transistor coupled to the word line, wherein the signal path does not pass through the first and second transistors.

20. The system of claim 19 , wherein, when the word line signal has a first value, the first MTJ element is switchable between a first resistance and a second resistance based on a value of the source line signal and a value of the bit line signal.

21. The system of claim 19 , further comprising a calibration circuit coupled to the resistor to control the bit line signal, the source line signal, and the word line signal to adjust a resistance of the resistor.

22. The system of claim 21 , wherein the circuit is a radio frequency circuit, a digital-to-analog conversion (DAC) circuit, an analog-to-digital conversion (ADC) circuit, a biasing circuit, or an input/output circuit.

23. The system of claim 19 , further comprising:
a display coupled to the processor; and
an antenna coupled to the processor to communicate over a wireless communication network.

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep P
• Ravi Ashoke
• Somasekhar Dinesh
• Balamurugan Ganesh
• Shekhar Sudip
• Musah Tawfiq
• Hsueh Tzu-Chien

Classifications

• G11C11/1659 Primary

  Cell access · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H03M1/765

  using a single level of switches which are controlled by unary decoded digital signals · CPC title

• H03H11/22

  providing two or more phase shifted output signals, e.g. n-phase output · CPC title