Exploiting frame-to-frame coherence for optimizing color buffer clear performance in graphics processing units

Patent metadata

Field	Value
Publication number	US-9589312-B2
Application number	US-201414577922-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein, includes allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), and rendering a first frame, wherein the first set of control bits are associated with the first frame. The method may further include allocating a second set of control bits associated with a second frame, and rendering the second frame. The method may further include facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames.

First claim

What is claimed is:

1. An apparatus comprising:
allocation/initialization logic to allocate and initialize a first set of control bits associated with a framebuffer in a graphics processing unit (GPU);
rendering logic to render a first frame, wherein the first set of control bits is associated with the first frame,
wherein the allocation/initialization logic is further to allocate a second set of control bits associated with a second frame,
wherein the rendering logic is further to render the second frame; and

expedited resolve logic to facilitate an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames,
wherein the first set of control bits is further associated with a set of cache lines, wherein the set of cache lines indicate at least one of cleared, rendered, and cleared-but-resolved, wherein a resolve operation is not necessitated when a cleared-but-resolved state is executed, wherein the set of cache lines refers to hardware added for the resolve operation when the framebuffer is first cleared.

2. The apparatus of claim 1 , further comprising normal resolve logic to facilitate a normal resolve operation of the first frame without the frame-to-frame coherence.

3. The apparatus of claim 1 , further comprising frame-to-frame coherence logic to determine the frame-to-frame coherence, wherein determining includes deducing a minimum set of resolve bits based on the first and second set of control bits associated with the first and second frames.

4. The apparatus of claim 1 , wherein facilitating the expedited resolve process is further based on the minimum set of resolve bits.

5. The apparatus of claim 1 , wherein the allocation/initialization logic is further to allocate and initialize enhanced control bits associated with the framebuffer.

6. The apparatus of claim 5 , wherein the rendering logic is further to render the first frame, and
wherein the normal resolve logic to facilitate a normal resolve process of the first frame without the frame-to-frame coherence.

7. The apparatus of claim 5 , further comprising clear logic to facilitate a clear operation to clear for the second frame, wherein the clear operation to initialize the enhanced control bits and set one or more control bits to the cleared-but-resolved state.

8. The apparatus of claim 5 , wherein the expedited resolve logic is further to facilitate a fast resolve operation of the second frame based on the enhanced control bits incorporating the frame-to-frame coherence.

9. A method comprising:
allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), wherein allocating further includes allocating a second set of control bits associated with a second frame;
rendering a first frame, wherein the first set of control bits are associated with the first frame, wherein rendering further includes rending the second frame; and
facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames,
wherein the first set of control bits is further associated with a set of cache lines, wherein the set of cache lines indicate at least one of cleared, rendered, and cleared-but-resolved, wherein a resolve operation is not necessitated when a cleared-but-resolved state is executed, wherein the set of cache lines refers to hardware added for the resolve operation when the framebuffer is first cleared.

10. The method of claim 9 , further comprising facilitating a normal resolve operation of the first frame without the frame-to-frame coherence.

11. The method of claim 9 , further comprising determining the frame-to-frame coherence, wherein determining includes deducing a minimum set of resolve bits based on the first and second set of control bits associated with the first and second frames.

12. The method of claim 9 , wherein facilitating the expedited resolve process is further based on the minimum set of resolve bits.

13. The method of claim 9 , wherein allocating and initializing further comprises allocating and initializing enhanced control bits associated with the framebuffer.

14. The method of claim 13 , further comprising:
rendering the first frame, and
facilitating a normal resolve process of the first frame without the frame-to-frame coherence.

15. The method of claim 13 , further comprising facilitating a clear operation to clear for the second frame, wherein the clear operation to initialize the enhanced control bits and set one or more control bits to the cleared-but-resolved state.

16. The method of claim 13 , further comprising facilitating a fast resolve operation of the second frame based on the enhanced control bits incorporating the frame-to-frame coherence.

17. At least one non-transitory machine-readable medium comprising a plurality of instructions, executed on a computing device, to facilitate the computing device to perform one or more operations comprising:
allocating and initializing a first set of control bits associated with a framebuffer in a graphics processing unit (GPU), wherein allocating further includes allocating a second set of control bits associated with a second frame;
rendering a first frame, wherein the first set of control bits are associated with the first frame, wherein rendering further includes rending the second frame; and
facilitating an expedited resolve operation of the second frame based on a frame-to-frame coherence associated with the first and second frames,
wherein the first set of control bits is further associated with a set of cache lines, wherein the set of cache lines indicate at least one of cleared, rendered, and cleared-but-resolved, wherein a resolve operation is not necessitated when a cleared-but-resolved state is executed, wherein the set of cache lines refers to hardware added for the resolve operation when the framebuffer is first cleared.

18. The non-transitory machine-readable medium of claim 17 , wherein the one or more operations comprise facilitating a normal resolve operation of the first frame without the frame-to-frame coherence.

19. The non-transitory machine-readable medium of claim 17 , wherein the one or more operations comprise determining the frame-to-frame coherence, wherein determining includes deducing a minimum set of resolve bits based on the first and second set of control bits associated with the first and second frames.

20. The non-transitory machine-readable medium of claim 17 , wherein facilitating the expedited resolve process is further based on the minimum set of resolve bits.

21. The non-transitory machine-readable medium of claim 17 , wherein allocating and initializing further comprises allocating and initializing enhanced control bits associated with the framebuffer.

22. The non-transitory machine-readable medium of claim 21 , wherein the one or more operations comprise:
rendering the first frame, and
facilitating a normal resolve process of the first frame without the frame-to-frame coherence.

23. The non-transitory machine-readable medium of claim 21 , herein the one or more operations comprise facilitating a clear operation to clear for the second frame, wherein the clear operation to initialize the enhanced control bits and set one or more control bits to the cleared-but-resolved state.

24. The non-transitory machine-readable medium of claim 21 , herein the one or

Assignees

• Intel Corp

Inventors

• Poddar Bimal

Classifications

• G06T1/60 Primary

  Memory management · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title