Accelerated interlane vector reduction instructions

Patent metadata

Field	Value
Publication number	US-9588766-B2
Application number	US-201213630154-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Sep 28, 2012
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of vector registers, wherein each vector register is divided into a plurality of lanes, and each lane stores a same number of data elements; and
execution circuitry coupled to the plurality of vector registers, the execution circuitry to:
receive a vector reduction instruction to reduce an array of the data elements stored in a source operand into a result in a destination operand using a reduction operator, wherein each of the source operand and the destination operand is one of the vector registers,
responsive to the vector reduction instruction, apply the reduction operator to two of the data elements in each lane, reduce the two data elements into one data element, and shift one or more remaining data elements when there is at least one of the data elements remaining in each lane;
wherein the execution circuitry is to convert reduction code without the vector reduction instruction into translated reduction code with the vector reduction instruction, wherein the reduction code and the translated reduction code specify a same sequence of reduction operations applied to the array of data elements across the plurality of lanes and generate a same result.

2. The apparatus of claim 1 , wherein the execution circuitry responsive to the vector reduction instruction is to insert a zero to a highest-order position in each lane.

3. The apparatus of claim 1 , wherein the reduction operator includes add, subtract or multiply.

4. The apparatus of claim 1 , wherein the execution circuitry is to apply the reduction operator to two of lowest-ordered data elements in each lane.

5. The apparatus of claim 1 , wherein the execution circuitry responsive to the vector reduction instruction is to shift each of the remaining data elements one position to the right within each lane.

6. The apparatus of claim 1 , wherein each of the data elements is a double-precision floating point number, a single-precision floating point number, or a half-precision floating point number.

7. A method comprising:
receiving a vector reduction instruction to reduce an array of the data elements stored in a source operand into a result in a destination operand using a reduction operator, wherein each of the source operand and the destination operand is one of a plurality of vector registers, each vector register being divided into a plurality of lanes, and each lane storing a same number of data elements;
responsive to the vector reduction instruction, applying the reduction operator to two of the data elements in each lane, reduce the two data elements into one data element;
shifting one or more remaining data elements when there is at least one of the data elements remaining in each lane; and
converting reduction code without the vector reduction instruction into translated reduction code with the vector reduction instruction, wherein the reduction code and the translated reduction code specify a same sequence of reduction operations applied to the array of data elements across the plurality of lanes and generate a same result.

8. The method of claim 7 , further comprising:
responsive to the vector reduction instruction, inserting a zero to a highest-order position in each lane.

9. The method of claim 7 , wherein the reduction operator includes add, subtract or multiply.

10. The method of claim 7 , wherein applying the reduction operator further comprises applying the reduction operator to two of lowest-ordered data elements in each lane.

11. The method of claim 7 , wherein shifting positions further comprises shifting each of the remaining data elements one position to the right within each lane.

12. The method of claim 7 , wherein each of the data elements is a double-precision floating point number, a single-precision floating point number, or a half-precision floating point number.

13. A system comprising:
memory; and
a processor coupled to the memory, the processor comprising:
a plurality of vector registers, wherein each vector register is divided into a plurality of lanes, and each lane stores a same number of data elements; and
execution circuitry coupled to the plurality of vector registers, the execution circuitry to:
receive a vector reduction instruction to reduce an array of the data elements stored in a source operand into a result in a destination operand using a reduction operator, wherein each of the source operand and the destination operand is one of the vector registers,
responsive to the vector reduction instruction, apply the reduction operator to two of the data elements in each lane, reduce the two data elements into one data element, and shift one or more remaining data elements when there is at least one of the data elements remaining in each lane;
wherein the execution circuitry is to convert reduction code without the vector reduction instruction into translated reduction code with the vector reduction instruction, wherein the reduction code and the translated reduction code specify a same sequence of reduction operations applied to the array of data elements across the plurality of lanes and generate a same result.

14. The system of claim 13 , wherein the execution circuitry responsive to the vector reduction instruction is to insert a zero to a highest-order position in each lane.

15. The system of claim 13 , wherein the reduction operator includes add, subtract or multiply.

16. The system of claim 13 , wherein the execution circuitry is to apply the reduction operator to two of lowest-ordered data elements in each lane.

17. The system of claim 13 , wherein the execution circuitry responsive to the vector reduction instruction is to shift each of the remaining data elements one position to the right within each lane.

Assignees

• Intel Corp

Inventors

• Caprioli Paul
• Kanhere Abhay S
• Cook Jeffrey J
• Al-Otoom Muawya M

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30038

  using a mask · CPC title