Vector find element not equal instruction

US9588762B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9588762-B2
Application numberUS-201213421442-A
CountryUS
Kind codeB2
Filing dateMar 15, 2012
Priority dateMar 15, 2012
Publication dateMar 7, 2017
Grant dateMar 7, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising: a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Find Element Not Equal operation; an extension field to be used in designating one or more registers; a first register field to designate a first register, the first register comprising a first operand; a second register field to designate a second register, the second register comprising a second operand; a third register field to designate a third register, the third register comprising a third operand; and a mask field, the mask field comprising one or more controls to be used during execution of the machine instruction; and executing the machine instruction, the execution comprising: identifying the first register based on a combination of the first register field and a first portion of the extension field, identifying the second register based on a combination of the second register field and a second portion of the extension field, and identifying the third register based on a combination of the third register field and a third portion of the extension field; searching the second operand for a zero element, wherein the searching the second operand for a zero element finds a zero element at a first byte position and the searching provides a null index set to a value that is a byte position of a sequentially-first zero element found in the search; comparing one or more elements of the second operand with one or more elements of the third operand for inequality, wherein the comparing finds an unequal element at a second byte position and the comparing provides a compare index separate from the null index, the compare index being set to a value that is a byte position of a sequentially-first unequal element; and selecting between the null index and the compare index to provide a result of executing the machine instruction, the result being the null index or the compare index and being a value of a byte position of a sequentially-first zero or unequal element or a value indicating a size of the second operand, and the selecting being based on whether an unequal element or zero element is found, wherein the selecting selects the lesser of the first byte position and the second byte position. 2. The computer program product of claim 1 , wherein the result is a byte index of an element, the element being a zero element or an unequal element, and the method further comprises: adjusting the result, the adjusting comprising performing at least one operation on the result to provide an adjusted result, the adjusted result comprising an index of a first byte of the element; and storing the adjusted result in the first operand. 3. The computer program product of claim 2 , wherein the machine instruction further comprises another mask field, the another mask field including an element size control, the element size control specifying a size of elements in at least one of the first operand, the second operand, or the third operand, and wherein the size is used in the adjusting. 4. The computer program product of claim 1 , wherein the result is a value indicating a size of the second operand, and the method further comprises storing the result in the first operand. 5. The computer program product of claim 1 , wherein the mask field comprises a condition code set control, and wherein the method comprises: determining whether the condition code set control is set; and based on the condition code set control being set, setting a condition code for execution of the machine instruction. 6. The computer program product of claim 5 , wherein the setting the condition code comprises one of: setting the condition code to a value indicating detection of a zero element in a lower indexed element than any unequal compares; setting the condition code to a value indicating a mismatch between an element of the second operand and an element of the third operand, and the element of the second operand is less than the element of the third operand; and setting the condition code to a value indicating a mismatch between an element of the second operand and an element of the third operand, and the element of the second operand is greater than the element of the third operand. 7. The computer program product of claim 1 , wherein the executing comprises determining, at runtime, a direction for the comparing, wherein the direction is one of left-to-right or right-to-left, and the determination comprises accessing by the machine instruction a direction control to determine the direction. 8. The computer program product of claim 1 , wherein the second operand and the third operand comprise N bytes, and wherein the comparing comprises comparing in parallel the N bytes of the second operand with the N bytes of the third operand, and wherein a size of an element comprises one of one byte, two bytes or four bytes. 9. The computer program product of claim 1 , wherein the value of the byte position of the zero element comprises a byte index, the byte index being an index of a first byte of the zero element. 10. The computer program product of claim 1 , wherein the value of the byte position of the unequal element comprises a byte index, the byte index being an index of a byte of the unequal element. 11. A computer system for executing a machine instruction in a central processing unit, the computer system comprising: a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Find Element Not Equal operation; an extension field to be used in designating one or more registers; a first register field to designate a first register, the first register comprising a first operand; a second register field to designate a second register, the second register comprising a second operand; a third register field to designate a third register, the third register comprising a third operand; and a mask field, the mask field comprising one or more controls to be used during execution of the machine instruction; and executing the machine instruction, the execution comprising: identifying the first register based on a combination of the first register field and a first portion of the extension field, identifying the second register based on a combination of the second register field and a second portion of the extension field, and identifying the third register based on a combination of the third register field and a third portion of the extension field; searching the second operand for a zero element, wherein the searching the second operand for a zero element finds a zero element at a first byte position and the searching provides a null index set to a value that is a byte position of a sequentially-first zero element found in the search; comparing one or more elements of the second operand with one or more elements of the third operand for inequality

Assignees

Inventors

Classifications

  • to perform operations on data operands · CPC title

  • comprising data of variable length · CPC title

  • according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

  • G06F9/3001Primary

    Arithmetic instructions · CPC title

  • Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9588762B2 cover?
Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vecto…
Who is the assignee on this patent?
Bradbury Jonathan D, Gschwind Michael K, Schwarz Eric M, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F9/3001. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).