Method of changing an operating frequency for performing a dynamic voltage and frequency scaling, system on-chip, and mobile device having the same

Patent metadata

Field	Value
Publication number	US-9588578-B2
Application number	US-201414532649-A
Country	US
Kind code	B2
Filing date	Nov 4, 2014
Priority date	Nov 11, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A method of changing an operating frequency for performing a dynamic voltage and frequency scaling on a central processing unit included in a system on-chip is provided. A previous maximum peak workload of the central processing unit is detected in a history period of the dynamic voltage and frequency scaling when the operating frequency of the central processing unit is determined to be increased, and an increased operating frequency is applied to the central processing unit. The increased operating frequency is calculated based on the previous maximum peak workload of the central processing unit.

First claim

What is claimed is:

1. A method of changing an operating frequency of a central processing unit included in a system on-chip, the method comprising:
receiving history information including a history of dynamic voltage and frequency scaling over a predetermined history period;
detecting a previous maximum peak workload of the central processing unit occurring when the operating frequency of the central processing unit has been increased from the history period of the received history information;
calculating an increased operating frequency of the central processing unit based on the detected previous maximum peak workload; and
setting the operating frequency of the central processing unit to the calculated increased operating frequency.

2. The method of claim 1 , further comprising: applying a maximum operating frequency of the central processing unit to the central processing unit when the previous maximum peak workload of the central processing unit is not detected in the history period.

3. The method of claim 1 , wherein the history period is between a first timing point and a second timing point, the second timing point being a timing point where the operating frequency of the central processing unit is determined to be increased, the first timing point being a timing point that is prior to the second timing point by a predetermined time.

4. The method of claim 3 , wherein the operating frequency of the central processing unit is increased when a workload ratio of the central processing unit is higher than a predetermined upper limit, wherein the operating frequency of the central processing unit is decreased when the workload ratio of the central processing unit is lower than a predetermined lower limit, and wherein the operating frequency of the central processing unit is maintained when the workload ratio of the central processing unit is between the predetermined upper limit and the predetermined lower limit.

5. The method of claim 3 , wherein a maximum value of previous peak workloads of the central processing unit is determined to be the previous maximum peak workload of the central processing unit when the previous peak workloads at previous timing points where the operating frequency of the central processing unit was increased are detected in the history period.

6. The method of claim 3 , wherein the increased operating frequency is calculated by multiplying a balance constant between performance and power consumption of the central processing unit, and the previous maximum peak workload of the central processing unit.

7. The method of claim 6 , wherein the increased operating frequency is adjusted by multiplying the increased operating frequency, and a tendency adjustment constant.

8. The method of claim 1 , wherein the system on-chip corresponds to an application processor included in a mobile device.

9. A system on-chip comprising;
at least one intellectual property unit;
a central processing unit configured to operate based on a clock signal;
a clock signal generating unit configured to generate the clock signal;
a monitoring unit configured to monitor a workload of the central processing unit;
a clock, signal management unit configured to increase an operating frequency of the central processing unit corresponding to a frequency of the clock signal when a workload ratio of the central processing unit is higher than a predetermined upper limit, to decrease the operating frequency of the central processing unit when the workload ratio of the central processing unit is lower than a predetermined lower limit, and to maintain the operating frequency of the central processing unit when the workload ratio of the central processing unit is between the predetermined upper limit and the predetermined lower limit; and
a history buffer unit configured to store previous peak workload data of the central processing unit at previous timing points where the operating frequency of the central processing unit was increased,
wherein the clock signal management unit detects a previous maximum peak workload of the central processing unit in the history buffer unit, and applies an increased operating frequency to the central processing unit when the clock signal management unit increases the operating frequency of the central processing unit, the increased operating frequency being calculated based on the previous maximum peak workload of the central processing unit.

10. The system on-chip of claim 9 , wherein the clock signal management unit applies a maximum operating frequency of the central processing unit to the central processing unit when the previous maximum peak workload of the central processing unit is not detected in the history buffer unit.

11. The system on-chip of claim 9 , wherein the history buffer unit is implemented as a queue having a predetermined capacity, and the history buffer unit operates a first-in first-out (FIFO) manner.

12. The system on-chip of claim 11 , wherein the history buffer unit stores data indicating ‘not-available’ instead of workload information of the central processing unit at previous timing points where the operating frequency of the central processing unit was maintained or decreased.

13. The system on-chip of claim 9 , wherein the increased operating frequency is calculated by multiplying a balance constant between performance and power consumption of the central processing unit, and the previous maximum peak workload of the central processing unit.

14. The system on-chip of claim 13 , wherein the increased operating frequency is adjusted by multiplying the increased operating frequency, and a tendency adjustment constant.

15. The system on-chip of claim 9 , wherein at least one of the clock signal generating unit, the monitoring unit, and the history buffer unit is included in the clock signal management unit.

16. A method for performing dynamic voltage and frequency scaling in a system-on-chip, comprising:
collecting history information including a history of dynamic voltage and frequency scaling performed over a predetermined history period;
attempting to identify a maximum peak workload occurring when the operating frequency of the system-on-chip has been increased from within the collected history information; and
increasing the operating frequency of the system-on-chip based on the identifying a maximum peak workload when a maximum peak workload has been identified.

17. The method of claim 16 , wherein the operating frequency of the system-on-chip is an operating frequency of a processor included within the system-on-chip.

18. The method of claim 16 , further comprising applying a maximum. operating frequency to the system-on-chip when a maximum peak workload has not been identified.

19. The method of claim 16 , wherein the predetermined history period is defined as predetermined length of time ending at a point in time where the operating frequency of the central processing unit is determined to be increased.

20. The method of claim 16 , wherein the increased operating frequency is calculated based on a power consumption of the system-on-chip, and the previous maximum peak workload.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jong-Lae
• Lee Hwang-Sub
• Noh Hee-Myung
• Kim Dong-Jin
• Lee Seung-Geun

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/32 Primary

  Means for saving power · CPC title