Electronic systems including heterogeneous multi-core processors and methods of operating same

Patent metadata

Field	Value
Publication number	US-9588577-B2
Application number	US-201414505952-A
Country	US
Kind code	B2
Filing date	Oct 3, 2014
Priority date	Oct 31, 2013
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

First claim

What is claimed is:

1. A method of operating an electronic system including a heterogeneous multi-core processor comprising a big core cluster comprising a plurality of big cores including a first big core and a second big core, and a little core cluster including a first little core and a second little core, wherein the first and second big cores are respectively high-performance/high-power consumption cores and the first and second little cores are respectively low-performance/low-power consumption cores, and wherein the first big core and first little core are mapped together as a first core pair and the second big core and second little core are mapped together as a second core pair, the method comprising:
measuring a temperature of the first big core using a temperature sensor;
switching at least one task from a first current core load assigned the first big core to the first little core when the measured temperature of the first big core exceeds a first temperature threshold;
switching at least one task from a second current core load assigned the second big core to the second little core, provided the second big core is physically adjacent to the first big core in the plurality of big cores, when the measured temperature of the first big core exceeds a second temperature threshold higher than the first temperature threshold;
applying respectively different dynamic voltage and frequency scaling (DVFS) tables to the first core pair and second core pair in response to a measured temperature for the first big core exceeding a first temperature threshold, and further in response to a determination that the second big core is physically adjacent to the first big core.

2. The method of claim 1 , further comprising:
wherein the switching of the at least one task from the first current core load to the first little core comprises in-kernel switching such that only one of the first big core and first little core in the first core pair is activated at any given time, and
the switching of the at least one task from the second current core load to the second little core comprises in-kernel switching such that only one of the second big core and second little core in the second core pair is activated at any given time.

3. The method of claim 1 , further comprising:
performing at least one of clock gating and power gating on at least one of the first big core and the second big core until the measured temperature of the first big core falls below a third temperature threshold less than the first temperature threshold.

4. The method of claim 3 , wherein the switching of the at least one task from the first current core load to the first little core comprises migrating a first job queue storing remaining tasks of the first current core load for the first big core to the first little core, and
the switching of the at least one task from the second current core load to the second little core comprises migrating a second job queue storing remaining tasks of the second current core load for the second big core to the second little core.

5. The method of claim 4 , wherein the migrating of the first job queue for the first big core to the first little core comprises swapping use of a first normal dynamic voltage and frequency scaling (DVFS) table for the first big core for use of a first throttled DVFS table defining a performance range for only the first little core, and
the migrating of the second job queue for the second big core to the second small core comprises swapping use of a second DVFS table for the second big core for use of a second throttled DVFS table defining a performance range for only the second little core.

6. The method of claim 5 , wherein the first normal DVFS table and the first throttled DVFS table are different from each other in defining respective performance ranges for the first little core, and
the second normal DVFS table and the second throttled DVFS table are different from each other in defining respective performance ranges for the second little core.

7. The method of claim 5 , wherein the first and second normal DVFS tables and the first and second throttled DVFS tables vary according to a number of activated big cores among a plurality of big cores in the heterogeneous multi-core processor.

8. The method of claim 1 , further comprising:
switching the first current core load from the first little core back to the first big core when the measured temperature of the first big core falls below a third temperature threshold; and
switching the second current core load from the second little core back to the second big core when the measured temperature of the first big core falls below a fourth temperature.

9. An electronic system comprising:
a heterogeneous multi-core processor comprising;
a plurality of big cores including a first big core and a second big core, and a plurality of little cores including a first little core and a second little core,
wherein the first big core and first little core are mapped together as a first core pair and the second big core and second little core are mapped together as a second core pair, and

the first big core and second big core are respectively high-performance and high-power consumption relative to the first little core and second little core; and
a kernel configured to respectively apply different dynamic voltage and frequency scaling (DVFS) tables to the first core pair and second core pair in response to a measured temperature for the first big core exceeding a first temperature threshold, and further in response to a determination that the second big core is physically adjacent to the first big core.

10. The electronic system of claim 9 , wherein the kernel is configured to apply a first normal DVFS table to the first core pair and a second normal DVFS table to the second core pair, so long as the measured temperature of the first big core remains less than or equal to the first temperature threshold, and
the kernel is further configured to apply a first throttled DVFS table to the first core pair and a second throttled DVFS table to the second core pair when the measured temperature of the first big core exceeds the first temperature threshold.

Assignees

• Ahn Min Seon
• Yu Ki Soo
• Kim Jae Choon
• Oh Chi Gwan
• Yim Myung Kyoon
• Samsung Electronics Co Ltd

Inventors

• Ahn Min Seon
• Yu Ki Soo
• Kim Jae Choon
• Oh Chi Gwan
• Yim Myung Kyoon

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/329

  by task scheduling · CPC title