Forming a solder joint between metal layers

Patent metadata

Field	Value
Publication number	US-9586281-B2
Application number	US-201514832044-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Aug 29, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

First claim

What is claimed is:

1. A method for forming a solder joint between metal layers, the method comprising:
preparing a structure having solder material placed between two metal layers; and
heating the structure to grow an intermetallic compound in a space between the two metal layers, wherein growing the intermetallic compound includes:
setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound;
setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and
maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

2. The method according to claim 1 , wherein the predetermined value for the temperature gradient is 0.1° C./μm.

3. The method according to claim 1 , wherein an average thickness of the intermetallic compound between the two metal layers is at least 10 μm.

4. The method according to claim 1 , wherein the two metal layers include Cu or Ni, and the solder material includes a Pb-free solder metal including Sn alone, Sn including at least one metal selected from a group including Ag, Au, Cu, Ni, Bi, In, Zn, Co, Ge, Fe and Ti, and In.

5. The method according to claim 1 , wherein preparing the structure further comprises:
preparing a first substrate having a plurality of first metal posts provided on a surface;
preparing a second substrate having a plurality of second metal posts aligned with the first metal posts provided on a surface, and having a solder material provided on the plurality of second metal posts; and
forming the structure by joining the plurality of first metal posts of the first substrate to the solder material on the plurality of second metal posts of the second substrate.

6. The method according to claim 5 , wherein the first substrate is a circuit board, and the second substrate is a semiconductor chip.

7. The method according to claim 6 , further comprising:
forming an underfill between the circuit board and the semiconductor chip.

8. A method for solder-joining a semiconductor chip to a semiconductor substrate, the method comprising:
preparing a circuit board having a plurality of first metal posts provided on a surface;
preparing a semiconductor chip having a plurality of second metal posts aligned with the first metal posts provided on the surface of the circuit board, and having a solder material provided on the plurality of second metal posts;
forming a structure by joining the plurality of first metal posts on the surface of the circuit board to the solder material on the plurality of corresponding second metal posts of the semiconductor chip; and
heating the structure to grow an intermetallic compound in a space between the plurality of first and corresponding second metal posts, wherein growing the intermetallic compound includes:
setting a first surface, in contact with the solder material between the plurality of first and corresponding second metal posts, to a first temperature, thereby enabling growth of the intermetallic compound;
setting a second surface, in contact with the solder material between the plurality of first and corresponding second metal posts, to a second temperature, wherein the second temperature is higher than the first temperature; and
maintaining a temperature gradient (temperature/unit thickness) between the plurality of first and corresponding second metal posts at a predetermined value or higher until the intermetallic compound substantially fills the space between the first and corresponding second metal posts.

9. The method according to claim 8 , wherein forming the structure further comprises:
forming an underfill between the circuit board and the semiconductor chip.

10. The method according to claim 8 , wherein the predetermined value for the temperature gradient is 0.1° C./μm.

11. The method according to claim 8 , wherein an average thickness of the intermetallic compound between the plurality of first and corresponding second metal posts is at least 10 μm.

12. The method according to claim 8 , wherein the plurality of first and corresponding second metal posts include Cu or Ni, and the solder material includes a Pb-free solder metal including Sn alone, Sn including at least one metal selected from a group including Ag, Au, Cu, Ni, Bi, In, Zn, Co, Ge, Fe and Ti, and In.

Assignees

• IBM

Inventors

• Aoki Toyohiro
• Horibe Akihiro
• Mori Hiroyuki
• Orii Yasumitsu
• Toriyama Kazushige
• Yang ting-li

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07221

  Aligning · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title