Semiconductor device including asymmetric electrode arrangement

Patent metadata

Field	Value
Publication number	US-9585197-B2
Application number	US-201414213030-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Aug 20, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Provided is a semiconductor device including an asymmetric electrode arrangement in which a plurality of electrodes are arranged asymmetrically in a vertical or horizontal direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface along an edge of the first side and a plurality of second electrodes arranged on the upper surface along an edge of the second side; and
a gap between the edge of the second side and the plurality of second electrodes is greater than a sum of a width of one of the first electrodes and a gap between the first electrodes and the edge of the first side.

2. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface along an edge of the first side and a plurality of third electrodes arranged on the upper surface along an edge of the third side; and
a gap between an electrode of the plurality of third electrodes that is closest to the second side and an edge of the second side is greater than a sum of a width of one of the plurality of first electrodes and a gap between the plurality of first electrodes and the edge of the first side.

3. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface along an edge of the first side and a plurality of third electrodes arranged on the upper surface along an edge of the third side; and
a gap between an electrode of the plurality of first electrodes that is closest to the fourth side and an edge of the fourth side is greater than a sum of a width of one of the plurality of third electrodes and a gap between the plurality of third electrodes and the edge of the third side.

4. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface in a first column and a plurality of second electrodes arranged on the upper surface in a second column; and
the first column and the second column are arranged in parallel along an edge of any one of the first side, the second side, the third side and the fourth side.

5. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface along an edge of the first side, a plurality of second electrodes arranged on the upper surface along an edge of the second side, a plurality of third electrodes arranged on the upper surface along an edge of the third side, and a plurality of fourth electrodes arranged on the upper surface along an edge of the fourth side; and
a gap between the edge of the second side and the plurality of second electrodes is greater than a sum of a width of one of the plurality of first electrodes and a gap between the plurality of first electrodes and the edge of the first side.

6. A semiconductor device comprising:
a semiconductor structure configured to perform a predetermined function; and
a plurality of electrodes arranged on the semiconductor structure,
wherein:
the plurality of electrodes are asymmetrically arranged in at least one of a first direction and a second direction;
the second direction is perpendicular to the first direction;
the semiconductor structure includes an upper surface opposite a lower surface, a first side and a second side facing each other in the first direction, and a third side and a fourth side facing each other in the second direction;
the plurality of electrodes comprise a plurality of first electrodes arranged on the upper surface along an edge of the first side, a plurality of second electrodes arranged on the upper surface along an edge of the second side, a plurality of third electrodes arranged on the upper surface along an edge of the third side, and a plurality of fourth electrodes arranged on the upper surface along an edge of the fourth side; and
a gap between the edge of the fourth side and the plurality of fourth electrodes is greater than a sum of a width of one of the plurality of third electrodes and a gap between the plurality of third electrodes and the edge of the third side.

7. A microheater comprising:
a semiconductor device including:
a semiconductor structure configured to perform a predetermined function, the semiconductor structure including an upper surface opposite a lower surface, a first side and a second side facing each other in a first direction, and a third side and a fourth side facing each other in a second direction;
first, third, and fifth electrodes arranged on the upper surface along an edge of the first side on the semiconductor structure; and
second, fourth, and sixth electrodes arranged on the upper surface along an edge of the second side on the semiconductor structure;
a metal thermal line connected between the first electrodes and the second electrodes in a zigzag pattern;
a variable resistive element positioned around a center of the semiconductor structure;
a first wiring connected between the third electrodes and the variable resistive

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Chin-Sung
• Chung Won-Seok

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/072

  of bump connectors · CPC title