Relay attack countermeasure system

Patent metadata

Field	Value
Publication number	US-9584542-B2
Application number	US-201514614038-A
Country	US
Kind code	B2
Filing date	Feb 4, 2015
Priority date	Feb 4, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

First claim

What is claimed is:

1. An apparatus for reducing the probability of a relay attack, comprising:
a microcontroller;
a receiver wherein the receiver receives a challenge message from a verifier, the challenge message having a challenge message frequency at a first challenge message frequency during a first time slot; and
a transmitter wherein the transmitter transmits a response message to the verifier, the response message having a response message frequency at a first response message frequency during the first time slot, the first response message frequency being different than the first challenge message frequency; wherein the probability of the relay attack is reduced as a result of the first response message frequency being different than the first challenge message frequency;
wherein the challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slot, the second challenge message frequency being different than the second response message frequency; wherein the probability of the relay attack is reduced as a result of the second response message frequency being different than the second challenge message frequency;
wherein the frequencies at which the response messages are sent are negotiated between the verifier and the transmitter prior to the first time slot; and
wherein the time slots when the response messages are sent are negotiated between the verifier and the transmitter prior to the first time slot.

2. The apparatus of claim 1 , wherein the first time slot has a duration that is different than a duration for the second time slot.

3. The apparatus of claim 1 , wherein the challenge message is received from the verifier continuously during the first time slot and the response message is transmitted continuously during the first time slot.

4. The apparatus of claim 1 , wherein the first and second challenge message frequencies and the first and second response message frequencies are negotiated with the verifier using encrypted messages.

5. The apparatus of claim 1 , wherein the verifier comprises a vehicle.

6. An apparatus for reducing the probability of a relay attack, comprising:
a microcontroller;
a receiver wherein the receiver receives, during a first time slot and a third time slot, a challenge message from a verifier at a first frequency; and
a transmitter wherein the transmitter transmits, during a second time slot, a response message to the verifier at the first frequency;
wherein each of the first, second, and third time slots have different durations; wherein the probability of the relay attack is reduced as a result of the first, second, and third time slots having different durations; and
wherein the transmitter is further configured to transmit a noise signal during a fourth time slot; wherein the probability of the relay attack is reduced as a result of the transmitting noise during the fourth time slot.

7. The apparatus of claim 6 wherein the transmitter is further configured to transmit the response message at a first power level during the second time slot and the noise signal at a second power level during the fourth time slot; wherein the probability of the relay attack is reduced as a result of transmitting the response message at the first power level during the second time slot and the noise signal at a second power level during the fourth time slot.

8. An apparatus for reducing the probability of a relay attack, comprising:
a microcontroller;
a receiver wherein the receiver receives, during a first time slot and a third time slot, a challenge message from a verifier at a first frequency; and
a transmitter configured to wherein the transmitter transmits, during a second time slot, a response message to the verifier at the first frequency;
wherein each of the first, second, and third time slots have different durations; wherein the probability of the relay attack is reduced as a result of the first, second, and third time slots having different durations;
wherein the duration of the first, second, and third time slots is less than a threshold value; and
wherein the transmitter is further configured to transmit a noise signal during a fourth time slot; wherein the probability of the relay attack is reduced as a result of the transmitting noise during the fourth time slot.

Assignees

• Texas Instruments Inc

Inventors

• Kim Hun-Seok
• Dabak Anand Ganesh
• Ren Jing-Fei
• Goel Manish

Classifications

• H04K3/86

  related to preventing deceptive jamming or unauthorized interrogation or access, e.g. WLAN access or RFID reading (record carriers with integrated circuit chips including means for preventing undesired reading or writing from or to record carriers by hindering electromagnetic reading or writing G06K19/07318; arrangements for sensing record carriers including arrangements for protecting the interrogation against piracy attacks G06K7/10257) · CPC title

• H04K3/65

  using deceptive jamming or spoofing, e.g. transmission of false signals for premature triggering of RCIED, for forced connection or disconnection to/from a network or for generation of dummy target signal · CPC title

• H04L2209/805

  Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor · CPC title

• H04K3/827

  using characteristics of target signal or of transmission (as countermeasure against jamming H04K3/25), e.g. using direct sequence spread spectrum or fast frequency hopping (spread spectrum techniques H04B1/69) · CPC title

• H04W12/12

  Detection or prevention of fraud · CPC title