Communication signal rate detection system
US-2016381584-A1 · Dec 29, 2016 · US
US9584240B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9584240-B2 |
| Application number | US-201313947415-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 22, 2013 |
| Priority date | Dec 13, 2007 |
| Publication date | Feb 28, 2017 |
| Grant date | Feb 28, 2017 |
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A network device provides output data rate control having variable bandwidth and a response time constant that increases according to an amount of time that an input rate of data to the network device is evaluated by the logic to provide output data rate control. The device applies a rate estimate when a determination of the output rate to a predetermined accuracy is unavailable.
Opening claim text (preview).
What is claimed is: 1. A network device for controlling an output data rate, the network device comprising non-transitory machine memory or circuits embodying logic to: provide output rate control for the network device, the output data rate control logic having variable bandwidth and an adjustable response time constant that increases according to an amount of time that an input rate of data to the network device is evaluated by the logic to provide output data rate control; and apply a rate estimate when a determination of the output data rate to a predetermined accuracy is unavailable. 2. The network device of claim 1 , further comprising logic to: set the response time constant to an initial value upon receiving a Program Clock Reference (PCR), and increase the response time constant until another PCR is received. 3. The network device of claim 1 , further comprising logic to: provide a control loop to determine an accumulated difference between packet input rate to the network device and packet output rate from the network device, and which controls the packet output rate to minimize said difference. 4. The network device of claim 3 , further comprising logic to: increase the response time constant of the logic to provide the control loop, the increase proportional to an amount of time the control loop is active. 5. The network device of claim 3 , further comprising logic to: limit the rate at which the packet output rate can change, and to reduce the control loop logic bandwidth as a result of the limit to the packet output rate. 6. The network device of claim 5 , further comprising logic to: track a time during which the control loop is active and in a mode where control loop logic bandwidth was reduced. 7. A process, comprising: controlling an output rate of a network device using rate control logic; providing a variable bandwidth for the rate control logic and increasing a response time constant of the rate control logic according to an increasing amount of time that an input rate of data to the network device is evaluated by the rate control logic; and applying a rate estimate to determine an output data rate, adjusting the output data rate based on an accumulated amount of time that the input rate of data is evaluated. 8. The process of claim 7 , further comprising: setting the response time constant to an initial value upon receiving a Program Clock Reference (PCR), and increasing the response time constant until another PCR is received. 9. The process of claim 7 , further comprising: employing control loop logic to determine an accumulated difference between packet input rate to the network device and packet output rate from the network device, and controlling the packet output rate to minimize said accumulated difference. 10. The process of claim 9 , further comprising: increasing the response time constant of the control loop logic to provide a control loop, the increase proportional to an amount of time the control loop is active. 11. The process of claim 9 , further comprising: limiting a rate at which the packet output rate can change, and reducing a control loop logic bandwidth as a result of a limit to the packet output rate. 12. The process of claim 11 , further comprising: tracking a time during which the control loop logic is active and in a mode where control loop logic bandwidth is reduced.
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