Isolator system supporting multiple ADCs via a single isolator channel

Patent metadata

Field	Value
Publication number	US-9584147-B2
Application number	US-201514831731-A
Country	US
Kind code	B2
Filing date	Aug 20, 2015
Priority date	Aug 22, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

In an isolation system, different analog to digital converters (“ADCs”) are provided on a first side of an isolation barrier. Outputs from the ADCs may be merged into a common data stream and communicated across the isolation barrier by a single isolation device. The ADCs may sample independent signals or may sample a common signal. When the ADCs sample a common signal, the system may monitor the input signal for fault conditions. During no fault operation, results of an analog-to-digital conversion may be communicated across an isolation barrier by an isolation device. During a fault condition, data representing the fault condition may replace the ADC data in communication across the isolation barrier. Fault conditions may be signaled by unique data patterns that can be distinguished from ADC data.

First claim

We claim:

1. An isolator system, comprising:
a plurality of analog to digital converters (ADCs), wherein at least two ADCs have different conversion times,
a signal combiner to merge outputs of the ADCs into a single data stream, and
a signal isolator, bridging an isolation barrier, to carry the merged data stream from a first side of the isolation barrier to a second side of the isolation barrier.

2. The system of claim 1 , wherein the ADCs have different signal bandwidths.

3. The system of claim 1 , wherein the ADCs have different resolutions of their digital outputs.

4. The system of claim 1 , wherein the ADCs have different noise floors.

5. The system of claim 1 , wherein the ADCs accept input signals having different spans.

6. The system of claim 1 , wherein the ADCs have architectures.

7. The system of claim 1 , wherein the ADCs generate multi-bit outputs of different bit widths.

8. The system of claim 1 , wherein the ADCs have inputs coupled to different signal sources.

9. The system of claim 1 , wherein the ADCs have inputs coupled to a common signal source.

10. The system of claim 9 , wherein the signal isolator transmits the merged data stream as a Manchester-coded signal in which:
data from a first ADC is represented according to Manchester-coding, and data from a second ADC, when the second ADC's output is in a predetermined state, replaces an instance of Manchester-coded output from the first ADC with a signaling pattern that is invalid under Manchester coding.

11. The system of claim 1 , wherein the signal isolator transmits the merged data stream as a run length limited coded signal.

12. The system of claim 1 , wherein the merged data stream includes data from the ADCs framed by a transmission gap of inactivity.

13. The system of claim 1 , wherein the merged data stream includes data from the ADCs framed by a header signal.

14. The system of claim 1 , further comprising a clock isolator that carries a clock signal from the second side of the isolation barrier to the first side of the isolation barrier.

15. The system of claim 1 , further comprising a transmit clock coupled to the combiner.

16. A method, comprising:
generating digital outputs from a plurality of analog-to-digital converters (ADCs), including generating multi-bit outputs of different bit widths using at least two ADCs,
merging the digital outputs from the ADCs into a single data stream,
generating an isolator signaling pattern from the merged data stream, and
transmitting the isolator signaling pattern across an isolation barrier.

17. The method of claim 16 , wherein the ADCs have different speeds in response to changing inputs.

18. The method of claim 16 , wherein the ADCs have different resolutions of their digital outputs.

19. The method of claim 16 , wherein the ADCs have different noise floors.

20. The method of claim 16 , wherein the ADCs accept input signals having different spans.

21. The method of claim 16 , rein the ADCs have different architectures.

22. The method of claim 16 , comprising:
coupling inputs of the ADCs to different signal sources.

23. The method of claim 16 , comprising:
coupling inputs of the ADCs to a common signal source.

24. The method of claim 23 , wherein the isolator signaling pattern is a Manchester-coded signal in which:
data from a first ADC is represented according to Manchester-coding, and data from a second ADC, when the second ADC's output is in a predetermined state, replaces an instance of Manchester-coded output from the first ADC with a signaling pattern that is invalid under Manchester coding.

25. The method of claim 16 , wherein the merged data stream is coded as a run length limited coded signal prior to generation of the isolator signaling pattern.

26. The method of claim 16 , wherein the isolator signaling pattern includes a gap of transmission inactivity that frames the outputs from the ADCs.

27. The method of claim 16 , wherein the isolator signaling pattern includes a header signal that frames the outputs from the ADCs.

28. The method of claim 16 , wherein the at least two ADCs include a first ADC and a second ADC, and wherein generating multi-bit outputs of different bit widths using at least two ADCs includes:
operating the first ADC according to a uniform quantization step size and operating the second ADC according to a non-uniform quantization step size.

29. The method of claim 16 , wherein the at least two ADCs include a first ADC and a second ADC, and wherein generating multi-bit outputs of different bit widths using at least two ADCs includes:
generating a first digital output of the first ADC at a first conversion rate and generating a second digital output of the second AI)C at a second conversion rate that is different from the first conversion rate.

30. The method of claim 16 , wherein transmitting the isolator signaling pattern across an isolation barrier includes:
asynchronously transmitting the isolator signaling pattern across an isolation barrier.

31. The isolator system of claim 1 , wherein the signal combiner is configured to asynchronously merge outputs of the ADCs into a single data stream.

32. The isolator system of claim 1 , wherein the at least two ADCs include a first ADC having a faster conversion rate than a conversion rate of a second ADC.

33. The isolator system of claim 32 , wherein the signal combiner is configured to merge output data from the first ADC representing a fault indication with output data from the second ADC.

34. The isolator system of claim 32 , wherein the signal combiner is configured to replace output data from the second ADC with output data from the first ADC representing a fault indication.

35. An isolator system, comprising:
a plurality of analog to digital converters (ADCs), wherein at least two ADCs have different signal bandwidths,
a signal combiner to merge outputs of the ADCs into a single data stream, and
a signal isolator, bridging an isolation barrier, to carry the merged data stream from a first side of the isolation barrier to a second side of the isolation barrier.

36. The isolator system of claim 35 , wherein the at least two ADCs include a first ADC and a second ADC, and wherein the first ADC is a sigma-delta ADC and the second ADC is a successive approximation register (SAR) ADC.

37. The isolator system of claim 35 , wherein the at least two ADCs include a first ADC having a faster conversion rate than a conversion rate of a second ADC.

38. An isolator system, comprising:
a plurality of analog to digital converters (ADCs), wherein at least two ADCs have different noise floors,
a signal combiner to merge outputs of the ADCs into a single data stream, and
a signal isolator, bridging an isolation barrier, to carry the merged data stream from a first side of the isolation barrier to a second side of the isolation barrier.

39. The isolator system of claim 38 , wherein the signal combiner is configured to synchronously merge outputs of the ADCs into a single data stream.

40. The isolator system of claim 38 , wherein the at least two ADCs include a first ADC and a second ADC, and wherein the fir

Assignees

• Analog Devices Global

Inventors

• Glibbery Adam
• O'Dowd John
• O'Byrne Nicola

Classifications

• H03M1/123 Primary

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/398

  among different converter types · CPC title

• H03M1/188

  Multi-path, i.e. having a separate analogue/digital converter for each possible range · CPC title

• H03M1/0604

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title