Converter controller with half bridge adaptive dead time circuit and method

Patent metadata

Field	Value
Publication number	US-9584045-B2
Application number	US-201214368351-A
Country	US
Kind code	B2
Filing date	Jan 5, 2012
Priority date	Jan 5, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The present disclosure relates to a controller, a circuit and method for controlling a power converter using pulse width modulation (PWM). At least one logic block ( 13, 15, 16 ) of the controller is configured to remove a command ( 4 ) which is configured to control the other power semiconductor switch ( 2 ) in a half-bridge ( 1,2 ) so that the other power semiconductor switch ( 2 ) remains in a non-conductive state while an antiparallel diode ( 6 ) allows an electric current ( 5 ) to pass in one direction, called the diode's forward direction, while blocking current in the opposite direction. In case the diode ( 6 ) is conducting instead of the other power semiconductor switch during the duration of the state of the command, the switching command ( 4 ) for the latter is omitted. The controller is further configured to modify the dead time interval (Tdead) between switching from the power semiconductor switch ( 3 ) to another power semiconductor switch ( 4 ) or vice versa in order to avoid a discontinuity in the transfer function ( 25 ).

First claim

What is claimed is:

1. A controller for a power converter using a pulse width modulation waveform, comprising:
a current level controller configured to detect a current; and
at least one control module, the control module configured to cause the controller to
generate a command for switching a first power semiconductor switch from a conductive state to a non-conductive state;
maintain the first power semiconductor switch in the non-conductive state for an off-time comprising a time when the pulse width modulation waveform is in an off state;
maintain a second power semiconductor switch in a non-conductive state during the off-time, based upon whether the detected current will remain in a same direction during all of a cycle period of the pulse width modulation waveform, wherein a diode allows an electric current to pass the second power semiconductor switch in one direction, while blocking current in an opposite direction;
generate a delay interval as a variable delay interval before switching of said first power semiconductor switch from the non-conductive state back to a conductive state; and
modify a duration of the variable delay interval in relation to the pulse width modulation waveform.

2. The controller according to claim 1 , wherein the controller is configured to remove said delay interval.

3. The controller according to claim 1 , wherein the controller is configured to modify duration of said variable delay interval in relation to a duty cycle of the pulse width modulation waveform.

4. The controller according to claim 1 , wherein the controller is configured to modify duration of said variable delay interval in relation to the time that the pulse width modulation waveform is in the off state.

5. The controller according to claim 1 , wherein the controller is configured to modify duration of said variable delay interval in relation to the time that the pulse width modulation waveform is in an on state.

6. The controller according to claim 1 , wherein the controller is configured to control said first power semiconductor switch so that the power semiconductor switches generate a pulse width modulation in relation to the command.

7. The controller according to claim 1 , wherein the controller is configured to receive the pulse width modulation waveform for controlling said first power semiconductor switch.

8. The controller according to claim 1 , wherein said diode is parallel coupled with the second power semiconductor switch.

9. The controller according to claim 1 , wherein the current level controller is configured to detect whether the detected current exceeds a threshold and to send the controller an allowance message to maintain the second power semiconductor switch in the non-conductive state.

10. A circuit, comprising the controller according to claim 1 , wherein at least one circuit block of said circuit comprises the at least one control module.

11. A controller for a power converter using a pulse width modulation waveform, comprising:
a current level controller configured to detect a current; and
at least one control module, the control module configured to cause the controller to
generate a command for switching a first power semiconductor switch from a conductive state to a non-conductive state;
maintain the first power semiconductor switch in the non-conductive state for an off-time comprising a time when the pulse width modulation waveform is in an off state;
maintain a second power semiconductor switch in a non-conductive state during the off-time, based upon the detected current, wherein a diode allows an electric current to pass the second power semiconductor switch in one direction, while blocking current in an opposite direction;
generate a delay interval as a variable delay interval before switching of said first power semiconductor switch from the non-conductive state back to a conductive state; and
modify a duration of said variable delay interval in relation to a function of said off-time, wherein the function comprises a constant value for the variable delay interval within a first predetermined interval defined by said off-time being lower than a minimum allowed pulse duration.

12. The controller according to claim 11 , wherein said function comprises said variable delay interval varying linearly with said off-time within a second predetermined interval defined at a lower end by said minimum allowed pulse duration.

13. The controller according to claim 11 , wherein the second power semiconductor switch is maintained in the non-conductive state based upon whether the detected current will remain in a same direction during all of a cycle period of the pulse width modulation waveform.

14. A method for controlling a power converter using pulse width modulation waveform, comprising:
generating a first command for switching a first power semiconductor switch from a conductive state to a non-conductive state;
detecting an output current;
maintaining a second power semiconductor switch in an open state during an off-time when the first power semiconductor switch is in the non-conductive state, based upon whether the output current will remain in a same direction during all of a cycle period of the pulse width modulation waveform;
allowing an electric current to pass the second power semiconductor switch in the open state in one direction, while blocking current in an opposite direction;
generating a delay interval as a variable delay interval before switching of said first power semiconductor switch from the non-conductive state back to a conductive state; and
modifying a duration of the delay interval in relation to the pulse width modulation waveform.

15. The method according to claim 14 , wherein modifying the duration of the delay interval includes removing the delay interval.

16. The method according to claim 14 , wherein modifying the duration of the delay interval includes modifying the duration in relation to a duty cycle of the pulse width modulation waveform.

17. The method according to claim 14 , wherein modifying the duration of the delay interval includes modifying the duration in relation to a time that the pulse width modulation waveform is in an off state.

18. The method according to claim 14 , wherein modifying the duration of the delay interval includes modifying the duration in relation to a time that the pulse width modulation waveform is in an on state.

19. The method according to claim 14 , wherein maintaining the second power semiconductor switch in the open state further includes maintaining the second power semiconductor switch in the open state based upon the output current exceeding a threshold.

Assignees

• Rozand Daniel
• Chambon Patrick
• De Cesaris Stefano
• Schneider Electric It Corp

Inventors

• Rozand Daniel
• Chambon Patrick
• De Cesaris Stefano

Classifications

• H02M1/38 Primary

  Means for preventing simultaneous conduction of switches · CPC title

• H02M7/5387 Primary

  in a bridge configuration · CPC title

• H02M2001/385

  Electricity · mapped topic

• H02M1/385

  with means for correcting output voltage deviations introduced by the dead time · CPC title