Tunable variable resistance memory device

US9583699B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9583699-B2
Application numberUS-201514962378-A
CountryUS
Kind codeB2
Filing dateDec 8, 2015
Priority dateJun 1, 2015
Publication dateFeb 28, 2017
Grant dateFeb 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The metal material may include tin. The device may also include a metal ion source structure between the chalcogenide glass layer and the second electrode. The device may include a buffer layer between the first electrode and the chalcogenide glass layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A variable resistance memory device comprising: a first electrode and a second electrode; a chalcogenide glass layer between the first electrode and the second electrode, the chalcogenide glass layer including a chalcogenide glass material co-deposited with a metal material; a metal ion source structure between the chalcogenide glass layer and the second electrode; a metal chalcogenide layer between the chalcogenide glass layer and the metal ion source structure; a buffer layer between the first electrode and the chalcogenide glass layer, wherein the buffer layer includes the chalcogenide glass material and excludes the metal material; and a second buffer layer between the chalcogenide glass layer and the metal chalcogenide layer. 2. The device of claim 1 , wherein the metal material includes tin. 3. The device of claim 2 , wherein the metal material includes chromium, tungsten, copper, cobalt, indium, or a combination thereof. 4. The device of claim 1 , wherein the chalcogenide glass material includes germanium selenide. 5. The device of claim 1 , wherein the metal ion source structure includes: a first adhesion layer and a second adhesion layer; and a mobile metal layer between the first adhesion layer and the second adhesion layer. 6. The device of claim 5 , wherein the first adhesion layer and the second adhesion layer include the chalcogenide glass material. 7. The device of claim 6 , wherein the mobile metal layer includes silver and wherein the second buffer layer includes the chalcogenide glass material and excludes the metal material. 8. The device of claim 7 , wherein the chalcogenide glass material includes germanium selenide. 9. The device of claim 5 , wherein the metal layer includes silver. 10. The device of claim 1 , wherein the metal chalcogenide layer includes tin-selenide. 11. The device of claim 1 , wherein a thickness of the metal chalcogenide layer is between 750 Å and 1250 Å. 12. The device of claim 1 , wherein a thickness of the chalcogenide glass layer is between 250 Å and 350 Å. 13. The device of claim 1 , wherein an electrical resistance between the first electrode and the second electrode is programmable within the range of 10 kΩ and 1 MΩ. 14. The device of claim 1 , wherein an electrical resistance between the first electrode and the second electrode is programmable within the range of 10 kΩ and 100 kΩ. 15. The device of claim 1 , wherein the second buffer layer includes the chalcogenide glass material and excludes the metal material. 16. The device of claim 15 , wherein the chalcogenide glass material includes germanium selenide. 17. A method of forming a variable resistance memory device, the method comprising: forming a first electrode; forming a buffer layer; forming a chalcogenide glass layer by co-depositing a chalcogenide glass material and a metal material, wherein the buffer layer is formed between the first electrode and the chalcogenide glass layer and the buffer layer includes the chalcogenide glass material and excludes the metal material; forming a second buffer layer, wherein the chalcogenide glass layer is formed between the buffer layer and the second buffer layer; forming a metal chalcogenide layer, wherein the second buffer layer is formed between the chalcogenide glass layer and the metal chalcogenide layer; forming an ion source structure, wherein the metal chalcogenide layer is formed between the ion source structure and the second buffer layer; and forming a second electrode, wherein the ion source structure is formed between the second electrode and the metal chalcogenide layer. 18. The method of claim 17 , wherein the metal material includes tin. 19. The method of claim 17 , wherein the metal material further includes a metal selected from the group consisting of chromium, tungsten, and copper, cobalt, indium, and combinations thereof. 20. The method of claim 17 , wherein forming the ion source structure comprises: forming a first adhesion layer; forming a metal layer; and forming a second adhesion layer.

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What does patent US9583699B2 cover?
A variable resistance memory device may include a first electrode and a second electrode. The device may further include a chalcogenide glass layer between the first electrode and the second electrode. The chalcogenide glass layer may include a chalcogenide glass material co-deposited with a metal material. The metal material may include tin. The device may also include a metal ion source struc…
Who is the assignee on this patent?
Univ Boise State
What technology area does this patent fall under?
Primary CPC classification H01L45/085. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).