Magnetic memory devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9583697-B2
Application number	US-201514716913-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	Aug 14, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The inventive concepts provide magnetic memory devices and methods forming the same. The method includes sequentially forming a first magnetic conductive layer and a capping layer on a substrate, patterning the capping layer and the first magnetic conductive layer to form a first magnetic conductive pattern and a capping pattern, forming an interlayer insulating layer exposing the capping pattern on the substrate, removing the capping pattern to expose the first magnetic conductive pattern, forming a tunnel barrier layer and a second magnetic conductive layer on the first magnetic conductive pattern and the interlayer insulating layer, and patterning the second magnetic conductive layer and the tunnel barrier layer to form a second magnetic conductive pattern and a tunnel barrier pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a contact plug pattern in a first interlayer dielectric layer formed on a substrate, top surfaces of the contact plug pattern and the first interlayer dielectric layer being substantially coplanar;
a first electrode pattern on the contact plug pattern and conductively coupled to the contact plug pattern;
a first magnetic conductive pattern on the first electrode pattern;
a second magnetic conductive pattern on the first magnetic conductive pattern;
a tunnel barrier pattern between the first magnetic conductive pattern and the second magnetic conductive pattern and having a first surface on which the second magnetic conductive pattern is formed and a second surface that is opposite the first surface; and
a metal oxide layer that is on a portion of the second surface of the tunnel barrier pattern that does not contact the first magnetic conductive pattern and that is adjacent, in a direction parallel to a top surface of the substrate, a side surface of a widest portion of the first magnetic conductive pattern,
wherein a bottom surface of the metal oxide layer is nearer the second surface of the tunnel barrier pattern than a bottom surface of the first magnetic conductive pattern.

2. The device according to claim 1 , wherein the first magnetic conductive pattern comprises a first portion that includes a portion of a first magnetic layer and a second portion that includes a portion of a magnetic recovery layer.

3. A semiconductor device comprising:
a contact plug pattern in a first interlayer dielectric layer formed on a substrate, top surfaces of the contact plug pattern and the first interlayer dielectric layer being substantially coplanar;
a first electrode pattern on the contact plug pattern and conductively coupled to the contact plug pattern;
a first magnetic conductive pattern on the first electrode pattern;
a second magnetic conductive pattern on the first magnetic conductive pattern;
a tunnel barrier pattern between the first magnetic conductive pattern and the second magnetic conductive pattern and having a first surface on which the second magnetic conductive pattern is formed and a second surface that is opposite the first surface; and
a metal oxide layer on a portion of the second surface of the tunnel barrier pattern that does not contact the first magnetic conductive pattern and on a side surface of a widest portion of the first magnetic conductive pattern;
wherein a bottom surface of the metal oxide layer is nearer the second surface of the tunnel barrier pattern than a bottom surface of the first magnetic conductive pattern,
wherein the first magnetic conductive pattern comprises a first portion that includes a portion of a first magnetic layer and a second portion that includes a portion of a magnetic recovery layer, and
wherein the magnetic recovery layer comprises a same material as the first magnetic layer and a reduced concentration of Boron (B) relative to the first magnetic layer.

4. The device according to claim 2 , wherein a portion of the magnetic recovery layer comprises an insulating material.

5. The device according to claim 2 , wherein the magnetic recovery layer includes a thickness in a range of about 1 Å to about 10 Å.

6. The device according to claim 2 , wherein the magnetic recovery layer includes a thickness in a range of about 1 Å to about 5 Å.

7. The device according to claim 1 , further comprising a second interlayer dielectric layer on the first interlayer dielectric layer,
wherein the metal oxide layer is on the second interlayer dielectric layer and includes an oxide of a magnetic conductive layer, and
wherein the second interlayer dielectric layer includes a non-metallic oxide, a non-metallic nitride and/or a non-metallic oxynitride.

8. The device according to claim 7 , wherein the non-metallic oxide, the non-metallic nitride and/or the non-metallic oxynitride comprise silicon oxide, silicon nitride and/or silicon oxynitride.

9. The device according to claim 1 , further comprising a second electrode pattern on the second magnetic conductive pattern,
wherein widths of the second electrode pattern, the second magnetic conductive pattern and the tunnel barrier pattern are greater than widths of the first electrode pattern and the first magnetic conductive pattern.

10. The device according to claim 1 , further comprising an insulating spacer on side walls of the first electrode pattern and the first magnetic conductive pattern.

11. The device according to claim 1 , further comprising a second interlayer dielectric layer on the first interlayer dielectric layer,
wherein a portion of the second interlayer dielectric layer is between the bottom surface of the first magnetic conductive pattern and the bottom surface of the metal oxide layer.

12. The device according to claim 11 , wherein the second interlayer dielectric layer contacts a sidewall of the first magnetic conductive pattern.

13. The device according to claim 2 , wherein the portion of the magnetic recovery layer extends along a top surface of the first magnetic conductive pattern.

14. The device according to claim 1 , wherein the first magnetic conductive pattern has a changeable magnetization direction.

15. The device according to claim 3 , wherein a portion of the magnetic recovery layer comprises an insulating material.

16. The device according to claim 3 , wherein the magnetic recovery layer has a thickness in a range of about 1 Å to about 10 Å.

17. The device according to claim 3 , further comprising a second interlayer dielectric layer on the first interlayer dielectric layer,
wherein the metal oxide layer is on the second interlayer dielectric layer and includes an oxide of a magnetic conductive layer, and
wherein the second interlayer dielectric layer includes a non-metallic oxide, a non-metallic nitride and/or a non-metallic oxynitride.

18. The device according to claim 17 , wherein the non-metallic oxide, the non-metallic nitride and/or the non-metallic oxynitride comprise silicon oxide, silicon nitride and/or silicon oxynitride.

19. The device according to claim 3 , further comprising a second electrode pattern on the second magnetic conductive pattern,
wherein widths of the second electrode pattern, the second magnetic conductive pattern and the tunnel barrier pattern are greater than widths of the first electrode pattern and the first magnetic conductive pattern.

20. The device according to claim 3 , further comprising a second interlayer dielectric layer on the first interlayer dielectric layer,
wherein a portion of the second interlayer dielectric layer is between the bottom surface of the first magnetic conductive pattern and the bottom surface of the metal oxide layer, and
wherein the second interlayer dielectric layer contacts a sidewall of the first magnetic conductive pattern.

Assignees

• Kim Keewon
• Kang Minah
• Park Soonoh
• Park Yong Sung
• Oh Sechung
• Samsung Electronics Co Ltd

Inventors

• Kim Keewon
• Kang Minah
• Park Soonoh
• Park Yong Sung
• Oh Sechung

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic