Methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-9583592-B2
Application number	US-201514697266-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Aug 4, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure. A nitridation process is performed on the first spacer layer. An upper portion of the substrate adjacent to the dummy gate structure is removed to form a trench. An inner wall of the trench is cleaned. An epitaxial layer is formed to fill the trench. The dummy gate structure is replaced with a gate structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a dummy gate structure on a substrate;
forming a spacer layer on the substrate to cover the dummy gate structure;
subsequently performing an implantation process comprising implanting impurities into an upper portion of the substrate using the dummy gate structure as a mask to thereby form an impurity region of the substrate adjacent to the dummy gate structure;
subsequently nitriding the spacer layer;
etching the nitrided spacer layer to form a spacer on a side surface of the dummy gate structure;
forming a trench in the substrate by removing an upper portion of the substrate adjacent to the dummy gate structure;
cleaning an interior surface that defines the trench;
forming an epitaxial layer in the trench; and
replacing the dummy gate structure with a gate structure.

2. The method of claim 1 , wherein the implantation process comprises:
forming a photoresist pattern on the substrate to expose a region including the dummy gate structure;
implanting the impurities into the upper portion of the substrate using both the photoresist pattern and the dummy gate pattern as a mask; and
removing the photoresist pattern by an ashing process and/or a stripping process.

3. The method of claim 2 , wherein the spacer layer is formed of silicon nitride, and wherein removing the photoresist pattern includes oxidizing the first spacer layer.

4. The method of claim 1 , wherein the nitriding is performed using nitrogen (N 2 ) and/or ammonia (NH 3 ).

5. The method of claim 1 , further comprising cleaning the spacer layer before the spacer layer is nitrided.

6. The method of claim 5 , wherein the cleaning of the spacer layer decreases the thickness of the spacer layer.

7. The method of claim 5 , wherein the cleaning is a dry cleaning process using gaseous ammonia (NH 3 ) and/or nitrogen trifluoride (NF 3 ) plasma, or a wet cleaning process using hydrogen fluoride (HF) and/or buffered oxide etch (BOE).

8. The method of claim 1 , further comprising cleaning the spacer layer after the spacer layer is nitrided.

9. The method of claim 1 , wherein the cleaning of the interior surface defining the trench is a wet etch process using ammonia hydroxide (NH 4 OH) as an etching solution.

10. The method of claim 1 , wherein the spacer layer is a first spacer layer, further comprising:
forming a second spacer layer on the first spacer layer after the first spacer layer is nitrided; and
anisotropically etching the first and second spacer layers to form first and second spacers, respectively, sequentially stacked on the side surface of the dummy gate structure.

11. The method of claim 10 , wherein the second spacer layer is formed of silicon nitride and to a thickness greater than that of the first spacer layer.

12. The method of claim 1 , wherein forming the dummy gate structure includes:
forming a dummy gate insulation layer of silicon oxide on the substrate;
forming a dummy gate electrode layer comprising polysilicon on the dummy gate insulation layer;
forming a hard mask of silicon nitride on the dummy gate electrode layer; and
sequentially etching the dummy gate electrode layer and the dummy gate insulation layer using the hard mask as an etching mask to form a dummy gate insulation layer pattern, a dummy gate electrode, and a hard mask sequentially stacked on the substrate.

13. The method of claim 12 , wherein forming the spacer comprises anisotropically etching the spacer layer, and
wherein replacing the dummy gate structure with the gate structure includes:
removing the hard mask, the dummy gate electrode and the dummy gate insulation layer pattern to form an opening exposing an inner wall surface of the spacer and a top surface of the substrate; and
forming a gate insulation layer pattern, a high-k dielectric layer pattern and a gate electrode that fill the opening and are sequentially stacked on the exposed top surface of the substrate.

14. The method of claim 13 , further comprising removing part of the exposed spacer to enlarge the opening.

15. The method of claim 14 , wherein removing the part of the first spacer to enlarge the opening comprises performing a dry process using gaseous ammonia (NH 3 ) and/or nitrogen trifluoride (NF 3 ) plasma, or a wet process using hydrogen fluoride (HF) and/or buffered oxide etch (BOE).

16. A method of manufacturing a semiconductor device, the method comprising:
forming first and second dummy gate structures on first and second regions, respectively, of a substrate;
forming a spacer layer on the substrate to cover the first and second dummy gate structures;
subsequently performing an implantation process comprising implanting impurities into an upper portion of the substrate using the dummy gate structures as a mask to thereby form first and second impurity regions of the substrate adjacent to the first and second dummy gate structures, respectively;
subsequently nitriding the spacer layer;
etching the nitrided spacer layer to form spacers on side surfaces of the first and second dummy gate structures, respectively;
forming a first trench in the substrate by removing an upper portion of the substrate adjacent to the first dummy gate structure;
cleaning an inner surface defining the first trench;
forming a first epitaxial layer in the first trench; and
replacing the first and second dummy gate structures with first and second gate structures, respectively.

17. The method of claim 16 , wherein the implantation process comprises:
forming a first photoresist pattern on the substrate to cover the second region;
forming the first impurity region at an upper portion of the first region of the substrate using both the first dummy gate pattern and the first photoresist pattern as a mask;
removing the first photoresist pattern by an ashing process and/or a stripping process;
forming a second photoresist pattern on the substrate to cover the first region;
forming the second impurity region at an upper portion of the second region of the substrate using both the second dummy gate pattern and the second photoresist pattern as a mask; and
removing the second photoresist pattern by an ashing process and/or a stripping process.

18. The method of claim 17 , wherein the spacer layer is formed of silicon nitride, and wherein removing the first photoresist pattern or removing the second photoresist pattern includes oxidizing the first spacer layer.

19. The method of claim 16 , wherein the spacer layer is a first spacer layer, and after nitriding the first spacer layer, further comprising:
forming a second spacer layer on the first spacer layer;
forming a third photoresist pattern on the substrate to cover the second region; and
anisotropically etching the first and second spacer layers to form first and second spacers sequentially stacked on the side surface of the first dummy gate structure.

20. The method of claim 19 , after forming the first epitaxial layer, further comprising:
forming a fourth photoresist pattern on the substrate to cover the first region;
anisotropically etching the first and second spacer layers to form third and fourth spacers sequentially stacked on the side surface of the second dummy gate structure;
forming a second trench in the substrate by removing one portion of said second impurity region of the substrate remote from the second dummy gate structure while leaving another portion of said second impurity region in place adjacent to

Assignees

• Park Pan-Kwi
• Shin Dong-Suk
• Won Seok-Jun
• Kim Weon-Hong
• Lee Jae-Gon
• Samsung Electronics Co Ltd

Inventors

• Park Pan-Kwi
• Shin Dong-Suk
• Won Seok-Jun
• Kim Weon-Hong
• Lee Jae-Gon

Classifications

• H10P70/20

  Cleaning during device manufacture · CPC title

• H10P14/6526

  introduced into an oxide material, e.g. changing SiO to SiON · CPC title

• H10P70/23 Primary

  during, before or after processing of insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title