Reduced scale resonant tunneling field effect transistor

Patent metadata

Field	Value
Publication number	US-9583566-B2
Application number	US-201514942274-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Dec 21, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

First claim

What is claimed is:

1. An apparatus comprising:
a p heterojunction tunneling field effect transistor (p-heTFET) including a source, a channel, and a drain; wherein:
(a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis;
(b) the channel length is less than 10 nm long, the channel width is less than 4 nm wide, and a channel height of the channel is less than 4 nm high;
(c) the source is negatively doped and has a first conduction band;
(d) the drain is positively doped and has a second conduction band with higher energy than the first conduction band;
(e) the source and the drain respectively include one of InAs and GaSb; Si and InAs; Si and SiGe;

GaAsSb and InAsSb; and InGaAs and InP.

2. The apparatus of claim 1 wherein the source includes InAs.

3. The apparatus of claim 2 wherein the drain includes GaSb.

4. The apparatus of claim 1 wherein the channel includes a nanowire.

5. The apparatus of claim 1 wherein the p-heTFET includes a subthreshold gate voltage to drain current ratio, which occurs between a transition from an off state to an on state, of less than 30 mV/dec.

6. The apparatus of claim 1 wherein a density of states (DOS) at a junction between the source and the channel includes a triangular projection misaligned with a valence band for the source in an off state and aligned with the valence band in an on state.

7. The apparatus of claim 1 wherein allowed electron energy states have a peak at a junction between the source and the channel in an on state.

8. The apparatus of claim 1 , comprising a heTFET on a substrate that also includes the p-heTFET, wherein the heTFET includes an additional source and an additional drain and the additional source has a conduction band with higher energy than a conduction band of the additional drain.

9. The apparatus of claim 1 wherein the source includes a material that is not included in the channel.

10. The apparatus of claim 1 wherein:
the source includes a first material and the channel includes a second material that is different from the first material; and
a heterojunction of the p-heTFET is located at an interface between the first and second materials.

11. The apparatus of claim 1 wherein:
the channel has a first cross-sectional area and is included in a nanowire;
the channel is between first and second sections of the nanowire; and
the first and second portions each have a cross-sectional area greater than the first cross-sectional area.

12. The apparatus of claim 1 wherein the source and the drain respectively include one of Si and InAs; Si and SiGe; GaAsSb and InAsSb; and InGaAs and InP.

13. An apparatus comprising:
a p heterojunction tunneling field effect transistor (p-heTFET) including a negatively doped source, a channel, and a positively doped drain; wherein:
a channel length of the channel is less than 10 nm long;
the drain has a conduction band with higher energy than a conduction band of the source; and
the source and the drain respectively include one of Si and InAs; Si and SiGe; GaAsSb and InAsSb; and InGaAs and InP.

14. The apparatus of claim 13 wherein a density of states (DOS) at a junction between the source and the channel includes a triangular projection misaligned with a valence band for the source in an off state and aligned with the valence band in an on state.

15. The apparatus of claim 14 wherein a channel width of the channel is less than 4 nm wide.

16. The apparatus of claim 13 wherein allowed electron energy states have a peak at a junction between the source and the channel in an on state.

17. The apparatus of claim 13 , wherein the p-heTFET includes a subthreshold gate voltage to drain current ratio, which occurs between a transition from an off state to an on state, of less than 30 mV/dec.

18. An apparatus comprising:
a substrate;
a first p heterojunction tunneling field effect transistor (p-heTFET) including a negatively doped first source, a first channel, and a positively doped first drain; wherein a first channel length of the first channel is less than 10 nm long, the first drain has a conduction band with higher energy than a conduction band of the first source, and the first p-heTFET is formed on the substrate; and
a second heTFET including a second source, a second channel, and a second drain; wherein the second drain has a conduction band with lower energy than a conduction band of the second source, and the second heTFET is formed on the substrate;
wherein the first source and the first drain respectively include one of InAs and GaSb; Si and InAs; Si and SiGe; GaAsSb and InAsSb; and InGaAs and InP.

19. The apparatus of claim 18 wherein the first p-heTFET includes a subthreshold gate voltage to drain current ratio, which occurs between a transition from an off state to an on state, of less than 30 mV/dec.

20. The apparatus of claim 18 wherein the first channel width is less than 4 nm wide.

Assignees

• Intel Corp

Inventors

• Avci Uygar E
• Nikonov Dmitri E
• Young Ian A

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0673 Primary

  Electricity · mapped topic

• H01L29/772

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic