Semiconductor device including magneto-resistive device

Patent metadata

Field	Value
Publication number	US-9583534-B2
Application number	US-201514795882-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Oct 31, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a cell transistor comprising a channel region, a first impurity region and a second impurity region, the first impurity region and the second impurity region being respectively arranged on both sides of the channel region in a channel direction of the cell transistor, the first impurity region and the second impurity region being asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape or an impurity concentration distribution, the first impurity region comprising a first hollow region formed in contact with a lower portion of a first source/drain region, and the first source/drain region and the first hollow region comprising different conductivity types;
a source line coupled to the first impurity region of the cell transistor; and
a magneto-resistive device coupled to the second impurity region of the cell transistor.

2. The semiconductor device of claim 1 , wherein a lowermost surface of the first impurity region is on a level that is lower than a lowermost surface of the second impurity region.

3. The semiconductor device of claim 1 , wherein the first impurity region and the second impurity region respectively comprise the first source/drain region and a second source/drain region that are symmetrical to each other about the center of the cell transistor in the channel direction.

4. The semiconductor device of claim 3 , wherein
the second impurity region further comprises second hollow region that is formed in contact with a lower portion of the second source/drain region, the second hollow region comprising a different conductivity type from the second source/drain region, and
an impurity concentration of the first hollow region is greater than an impurity concentration of the second hollow region.

5. The semiconductor device of claim 3 , wherein
the first impurity region and the second impurity region respectively comprise first and second Lightly Doped Drain (LDD) regions that respectively extend from the first and second source/drain regions toward the channel region, the first and second LDD regions comprising a same conductivity type as the first and second source/drain regions, and
the first LDD region and the second LDD region are asymmetrical in terms of at least one a shape or an impurity concentration distribution about the center of the cell transistor in the channel direction.

6. The semiconductor device of claim 5 , wherein an impurity concentration of each of the first and second LDD regions is less than an impurity concentration of each of the first and second source/drain regions.

7. The semiconductor device of claim 5 , wherein the impurity concentration of the first LDD region is less than the impurity concentration of the second LDD region.

8. The semiconductor device of claim 1 , wherein a threshold voltage of the cell transistor for a current flow in a direction from the first impurity region to the second impurity region is less than a threshold voltage of the cell transistor for a current flow in a direction from the second impurity region to the first impurity region.

9. The semiconductor device of claim 8 , wherein the cell transistor is an n-type metal oxide semiconductor field effect transistor (n-MOSFET).

10. A semiconductor device, comprising:
first and second cell transistors, the first and second cell transistors comprising a common impurity region, a first individual impurity region and a second individual impurity region, the common impurity region comprising a first end and a second end, a first channel region being disposed between the first end of the common impurity region and the first individual impurity region and a second channel region being disposed between the second end of the common impurity region and the second individual impurity region, the first end of the common impurity region and the first individual impurity region being asymmetrical to each other about a center of the first channel region with respect to at least one of a shape, an impurity concentration distribution about a center of the channel region of the first individual impurity region in the channel direction, and the second end of the common impurity region and the second individual impurity region being asymmetrical to each other about a center of the second channel region with respect to at least one of a shape and an impurity concentration distribution, the common impurity region comprising first and second hollow regions respectively formed in contact with the first end and the second end of a lower portion of a common source/drain region, and the first and second hollow regions respectively facing the first and second individual impurity regions;
a source line coupled to the common impurity region; and
first and second magneto-resistive devices respectively coupled to the first and second individual impurity regions.

11. The semiconductor device of claim 10 , wherein
the common impurity region, the first individual impurity region, and the second individual impurity region respectively comprise the common source/drain region, a first individual source/drain region, and a second individual source/drain region each having lowermost surfaces that are on an identical level.

12. The semiconductor device of claim 11 , wherein
the first and second individual impurity regions respectively further comprise third and fourth hollow regions respectively formed in contact with respective lower portions of the first and second source/drain regions, the third and fourth hollow regions respectively facing the common impurity region, and
an impurity concentration of each of the first and second hollow regions is greater than an impurity concentration of each of the third and fourth hollow regions.

13. A semiconductor device, comprising:
a cell region comprising a cell transistor, a source line and a magneto-resistive device, the cell transistor comprising a cell channel region, a first cell impurity region and a second cell impurity region that are arranged on both sides of the cell channel region in a channel direction, the source line being coupled to the first cell impurity region, and the magneto-resistive device being coupled to the second cell impurity region, and the first cell impurity region and the second cell impurity region being asymmetrical to each other about a center of the cell transistor in a cell channel direction with respect to at least one of a shape or an impurity concentration distribution; and
a logic region comprising a logic transistor, the logic transistor comprising a logic channel region, a first logic impurity region and a second logic impurity region that are arranged on both sides of the logic channel region in a channel direction, and the first logic impurity region and the second logic impurity region being substantially symmetrical to each other about a center of the logic transistor in a logic channel direction.

14. The semiconductor device of claim 13 , wherein
the first cell impurity region and the second cell impurity region respectively comprise first and second cell source/drain regions that are substantially symmetrical to each other about the center of the cell transistor in the cell channel direction, and
the first logic impurity region and the second logic impurity region respectively comprise first and second logic source/drain regions that are symmetrical to each other about the center of the logic transistor in the logic channel direction.

15. The semiconductor device of claim 14 , wherein
the first and second cell impurity regions f

Assignees

• Lee Choong-Jae
• Min Hong-Kook
• Seo Bo-Young
• Ivaniukovich Aliaksei
• Lee Yong-Kyu
• Samsung Electronics Co Ltd

Inventors

• Lee Choong-Jae
• Min Hong-Kook
• Seo Bo-Young
• Ivaniukovich Aliaksei
• Lee Yong-Kyu

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/7833

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H01L29/1045

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic