Process for transferring circuit layer

Patent metadata

Field	Value
Publication number	US-9583531-B2
Application number	US-201414899243-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 19, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, the routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.

First claim

The invention claimed is:

1. A process for transferring a buried circuit layer to a receiver substrate, the process comprising:
providing a donor substrate comprising an internal etch stop zone and covered on a front side of the donor substrate with a circuit layer;
producing over an entire circumference of the donor substrate, on the front side covered with the circuit layer, either a peripheral trench that extends at a distance from a lateral edge of the donor substrate, or a peripheral routing, the routing or the trench being produced over a depth such that the routing or the trench passes entirely through the circuit layer and extend into the donor substrate;
depositing on an exposed side of the circuit layer and on the routed side or on the walls of the trench, a second stop layer comprising a stop material that is selective with respect to etching of the circuit layer without filling the trench;
bonding the receiver substrate to the donor substrate on the side of the donor substrate covered by the second stop layer; and
thinning the donor substrate by chemical etching of a back side of the donor substrate, until the etch stop zone is reached, so as to obtain transfer of the buried circuit layer to the receiver substrate.

2. The process of claim 1 , wherein the etch stop zone comprises a first stop layer including a material that is selective with respect to etching of the material of the of the donor substrate.

3. The process of claim 2 , wherein the peripheral routing or the peripheral trench has a depth such that it passes through the etch stop zone without penetrating into a back portion or a back layer of the donor substrate.

4. The process of claim 1 , wherein the donor substrate includes a doped front layer and a non-doped back layer, and wherein the etch stop zone comprises an interface between the doped front layer and the non-doped back layer of the donor substrate.

5. The process of claim 4 , wherein the peripheral routing or the peripheral trench has a depth such that it passes through the etch stop zone without penetrating into a back portion or a back layer of the donor substrate.

6. The process of claim 1 , wherein the peripheral routing or the peripheral trench has a depth such that it passes through the etch stop zone without penetrating into a back portion or a back layer of the donor substrate.

7. The process of claim 1 , wherein the peripheral routing or the peripheral trench is produced over a depth such that it does not pass through the etch stop zone and wherein, after the chemical etching of the back side of the donor substrate, an additional step of mechanical removal of a residual peripheral ring of the donor substrate is carried out.

8. The process of claim 7 , wherein the mechanical removal of the residual peripheral ring of the donor substrate is carried out by grinding or chemical mechanical polishing (CMP).

9. The process of claim 1 , wherein the peripheral routing or the peripheral trench has a depth such that it passes through the etch stop zone and extends into a back portion or a back layer of the donor substrate and wherein, after the chemical etching of the back side of the donor substrate, an additional step of mechanical removal of a residue of the second stop layer is carried out.

10. The process of claim 9 , wherein the mechanical removal of the residue of the second stop layer is carried out by grinding or chemical mechanical polishing (CMP).

11. The process of claim 1 , wherein the second stop layer is deposited by chemical vapor deposition (CVD) or spin coating.

12. The process of claim 1 , wherein the peripheral trench is produced with the aid of at least one of laser etching, dry etching and wet etching.

13. The process of claim 1 , wherein the peripheral trench is located at a distance from the lateral edge of the donor substrate of less than or equal to 5 mm.

14. The process of claim 1 , wherein a width of the trench is between 10 μm and 500 μm.

15. The process of claim 1 , wherein the materials of the first stop layer and the second stop layer are oxides or nitrides.

16. The process of claim 15 , wherein the materials of the first stop layer and the second stop layer are individually selected from the group consisting of silicon oxide (SiO 2 ), silicon oxynitride (SiO x N y ) and silicon oxycarbide (SiO x C y ).

17. The process of claim 1 , wherein the materials of the first stop layer and the second stop layer are identical.

18. The process of claim 1 , wherein the donor substrate comprises a semiconductor material.

19. The process of claim 1 , wherein the bonding of the donor substrate and the receiver substrate takes place by molecular adhesion.

Assignees

• Soitec Silicon On Insulator

Inventors

• Broekaart Marcel
• Marinier Laurent

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/00

  Package configurations · CPC title

• H01L2924/00

  Electricity · mapped topic