Solid-state image pickup element and solid-state image pickup element mounting structure

US9583526B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9583526-B2
Application numberUS-201214116852-A
CountryUS
Kind codeB2
Filing dateJun 19, 2012
Priority dateSep 5, 2011
Publication dateFeb 28, 2017
Grant dateFeb 28, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

First claim

Opening claim text (preview).

The invention claimed is: 1. A solid-state image pickup element mounting structure comprising: a solid-state image pickup element comprising: a semiconductor substrate having a photosensitive region, a CCD being formed as pixels in the photosensitive region; a plurality of first electrode pads arranged in a first array in a first direction on a principal face of the semiconductor substrate; a plurality of second electrode pads arranged in a second array in the first direction on the principal face of the semiconductor substrate; a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence, and wherein the plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line of the first and second arrays, wherein the center line is perpendicular to the first direction, and the first array and the second array are separately arranged; wherein the semiconductor substrate has a light receiving surface side defined on the principal face side, a mounting member on which the solid-state image pickup element is mounted and in which a plurality of third electrode pads are arranged on a principal face thereof, wherein the solid-state image pickup element is mounted on the mounting member so that the back face to the principal face of the solid-state image pickup element is opposite to the principal face of the mounting member, and wherein the plurality of first electrode pads and the plurality of third electrode pads are connected by wire bonding. 2. The solid-state image pickup element mounting structure according to claim 1 , wherein the plurality of first electrode pads are located nearer to an edge of the semiconductor substrate than the plurality of second electrode pads. 3. A solid-state image pickup element mounting structure comprising: a solid-state image pickup element comprising: a semiconductor substrate having a photosensitive region, a CCD being formed as pixels in the photosensitive region; a plurality of first electrode pads arranged in a first array in a first direction on a principal face of the semiconductor substrate; a plurality of second electrode pads arranged in a second array in the first direction on the principal face of the semiconductor substrate; a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence, and wherein the plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line of the first and second arrays, wherein the center line is perpendicular to the first direction, and the first array and the second array are separately arranged; wherein the semiconductor substrate has a light receiving surface side defined on the back face side to the principal face, a mounting member on which the solid-state image pickup element is mounted and in which a plurality of third electrode pads are arranged on a principal face thereof, wherein the solid-state image pickup element is mounted on the mounting member so that the principal face of the solid-state image pickup element is opposite to the principal face of the mounting member, and wherein the plurality of second electrode pads and the plurality of third electrode pads are connected by flip chip bonding. 4. The solid-state image pickup element mounting structure according to claim 3 , wherein the plurality of first electrode pads are located nearer to an edge of the semiconductor substrate than the plurality of second electrode pads. 5. A solid-state image pickup element mounting structure comprising: a solid-state image pickup element comprising: a semiconductor substrate having a photosensitive region, a CCD being formed as pixels in the photosensitive region; a plurality of first electrode pads arranged in a first array in a first direction on a principal face of the semiconductor substrate; a plurality of second electrode pads arranged in a second array in the first direction on the principal face of the semiconductor substrate; a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence, and wherein the plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line of the first and second arrays, wherein the center line is perpendicular to the first direction, and the first array and the second array are separately arranged wherein the semiconductor substrate has a light receiving surface side defined on the back face side to the principal face, a mounting member on which the solid-state image pickup element is mounted and in which a plurality of third electrode pads are arranged on a principal face thereof, wherein the solid-state image pickup element is mounted on the mounting member so that the principal face of the solid-state image pickup element is opposite to a back face to the principal face of the mounting member, and wherein the plurality of second electrode pads and the plurality of third electrode pads are connected by wire bonding. 6. The solid-state image pickup element mounting structure according to claim 5 , wherein the plurality of first electrode pads are located nearer to an edge of the semiconductor substrate than the plurality of second electrode pads. 7. A solid-state image pickup element mounting structure comprising: a solid-state image pickup element comprising: a semiconductor substrate of a rectangular shape having a photosensitive region, a CCD being formed as pixels in the photosensitive region; a plurality of first electrode pads linearly disposed in a first array on a principal face of the semiconductor substrate and symmetrically distributed about a center line of the first array; a plurality of second electrode pads linearly disposed in a second array parallel to the first array on the principal face of the semiconductor substrate and symmetrically distributed about the center line; a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence, and wherein the plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in an identical order relation in an array order in a first direction and in an array order in a second direction opposite to the first direction, and so that each interconnection spans the center line, wherein the semiconductor substrate has a light receiving surface side defined on the principal face side, a mounting member on which the solid-state image pickup element is mounted and in which a plurality of third electrode pads are arranged on a principal face thereof, wherein the solid-state image pickup element is mounted on the mounting member so that the back face to the principal face of the solid-state image pickup element is opposite to the principal face of the mounting member, and wherein the plurality of first electrode pads and the plurality of third electrode pads are connected by wire bonding. 8. The solid-state image pickup element mounting structure according to claim 7 , wherein t

Assignees

Inventors

Classifications

  • Vias, e.g. via plugs · CPC title

  • comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

  • Die-attach connectors and bond wires · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

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What does patent US9583526B2 cover?
A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate,…
Who is the assignee on this patent?
IKEYA Tomohiro, Fukui Toshiyuki, Suzuki Hisanori, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10F39/804. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).