Integrated circuit module having a first die with a power amplifier stacked with a second die and method of making the same

US9583471B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9583471-B2
Application numberUS-201514595451-A
CountryUS
Kind codeB2
Filing dateJan 13, 2015
Priority dateJan 13, 2014
Publication dateFeb 28, 2017
Grant dateFeb 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is an integrated circuit module that includes a first die having a plurality of hot regions and at least one cool region when operating under normal conditions. The first die with a top surface includes at least one power amplifier that resides in the plurality of hot regions. The integrated circuit module also includes a second die. The second die has a bottom surface, which is adhered to the top surface of the first die, wherein any portion of the bottom surface of the second die that is adhered to the top surface of the first die resides exclusively on the at least one cool region. In at least one embodiment, the first die is an RF power amplifier die and the second die is a controller die having control circuitry configured to control the at least one power amplifier that is an RF power amplifier type.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit module comprising: an RF power amplifier die having a plurality of hot regions and at least one cool region when operating under normal conditions, the RF power amplifier die having at least one RF power amplifier that resides in the plurality of hot regions and a top surface; and a controller die having control circuitry configured to control the at least one RF power amplifier and a bottom surface, which is adhered to the top surface of the RF power amplifier die with non-conductive adhesive, wherein any portion of the bottom surface of the controller die that is adhered to the top surface of the RF power amplifier die resides exclusively on the at least one cool region. 2. The integrated circuit module of claim 1 wherein all of the bottom surface of the controller die is adhered to the top surface of the RF power amplifier die to reside exclusively on the at least one cool region. 3. The integrated circuit module of claim 1 wherein only a first portion of the bottom surface of the controller die is adhered to the top surface of the RF power amplifier die to reside exclusively on the at least one cool region, and a second region of the controller die hangs over a peripheral edge of the RF power amplifier die. 4. The integrated circuit module of claim 1 further including a first plurality of electrically conductive pads on an exposed portion of the top surface of the RF power amplifier die and a second plurality of electrically conductive pads on a top surface of the controller die with at least one bonding wire extending between at least one of the first plurality of electrically conductive pads and the at least one of the second plurality of electrically conductive pads. 5. The integrated circuit module of claim 1 wherein a passivation layer comprises the top surface of the RF power amplifier die. 6. The integrated circuit module of claim 5 wherein the passivation layer ranges in thickness from around about 5 μm to around about 10 μm. 7. The integrated circuit module of claim 1 wherein the RF power amplifier die comprises gallium arsenide (GaAs) technology. 8. The integrated circuit module of claim 1 wherein the controller die comprises silicon (Si) technology. 9. The integrated circuit module of claim 8 wherein the controller die further comprises complementary metal oxide semiconductor (CMOS) technology. 10. The integrated circuit module of claim 1 wherein the plurality of hot regions and the at least one cool region when operating under normal conditions has a temperature difference that ranges from around about 40° C. to around about 90° C. 11. A method of making an integrated circuit module comprising: providing an RF power amplifier die having a plurality of hot regions and at least one cool region when operating under normal conditions, the RF power amplifier die having a top surface and at least one RF power amplifier that resides in the plurality of hot regions; providing a controller die having a bottom surface and control circuitry configured to control the at least one RF power amplifier; determining a location of the at least one cool region of the RF power amplifier die; and adhering the bottom surface of the controller die to the top surface of the RF power amplifier die with non-conductive adhesive such that any portion of the bottom surface that is adhered to the top surface of the RF power amplifier die resides exclusively on the at least one cool region. 12. The method of making the integrated circuit module of claim 11 wherein the bottom surface of the controller die is adhered to the top surface of the RF power amplifier die such that all of the bottom surface of the controller die resides exclusively on the at least one cool region. 13. The method of making the integrated circuit module of claim 11 wherein only a first portion of the bottom surface of the controller die is adhered to the top surface of the RF power amplifier die to reside exclusively on the at least one cool region, and a second region of the controller die hangs over a peripheral edge of the RF power amplifier die. 14. The method of making the integrated circuit module of claim 11 further including bonding at least one of a first plurality of electrically conductive pads on an exposed portion of the top surface of the RF power amplifier die to at least one of a second plurality of electrically conductive pads on a top surface of the controller die with at least one bonding wire. 15. The method of making the integrated circuit module of claim 11 further including disposing a passivation layer onto the RF power amplifier die to fabricate the top surface of the RF power amplifier die. 16. The method of making the integrated circuit module of claim 11 wherein the passivation layer ranges in thickness from around about 5 μm to around about 10 μm. 17. The method of making the integrated circuit module of claim 11 wherein determining the location of the at least one cool region of the RF power amplifier die ensures that a temperature difference that ranges from around about 40° C. to around about 90° C. is established between the plurality of hot regions and the at least one cool region when the integrated circuit module is operating under normal conditions. 18. The method of making the integrated circuit module of claim 11 wherein the RF power amplifier die comprises gallium arsenide (GaAs) technology. 19. The method of making the integrated circuit module of claim 11 wherein the controller die comprises Si technology. 20. The method of making the integrated circuit module of claim 19 wherein the controller die further comprises CMOS technology.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

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What does patent US9583471B2 cover?
Disclosed is an integrated circuit module that includes a first die having a plurality of hot regions and at least one cool region when operating under normal conditions. The first die with a top surface includes at least one power amplifier that resides in the plurality of hot regions. The integrated circuit module also includes a second die. The second die has a bottom surface, which is adher…
Who is the assignee on this patent?
Rf Micro Devices Inc, Qorvo Us Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).