Electronic device with solder pads including projections

Patent metadata

Field	Value
Publication number	US-9583470-B2
Application number	US-201314135209-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Dec 19, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.

First claim

The invention claimed is:

1. An IC package, comprising:
at least one semiconductor chip coupled to one or more opposing surfaces through a number of solder balls;
one or more projections extending from at least one of the one or more opposing surfaces including a number of electrical connection pads, the connection pads including a substantially planar top surface having a first surface area, wherein the one or more projections occupy only a fraction of the first surface area, wherein the one or more projections penetrates into a corresponding solder ball wherein the one or more projections include a number of openings within the one or more projections that increase a surface area of the one or more projections and absorb excess solder, wherein the number of openings includes a mesh of wires.

2. The IC package of claim 1 , wherein the one or more opposing surfaces include a package substrate.

3. The IC package of claim 2 , wherein the semiconductor chip includes a processor chip.

4. The IC package of claim 3 , wherein the one or more opposing surfaces include an embedded bridge.

5. The IC package of claim 1 , wherein the one or more projections extend from connection pads on only the semiconductor chip in the given pair.

6. The IC package of claim 1 , wherein the one or more projections extend from connection pads on only the one or more opposing surfaces in the given pair.

7. The IC package of claim 4 , further including a memory chip mounted adjacent to the processor chip, wherein the memory chip is coupled to the processor chip through the embedded bridge.

8. The IC package of claim 1 , wherein the one or more projections extend from both connection pads in the given pair.

Assignees

• Intel Corp

Inventors

• Karhade Omkar
• Deshpande Nitin

Classifications

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title