Systems and methods for high-speed, low-profile memory packages and pinout designs

Patent metadata

Field	Value
Publication number	US-9583452-B2
Application number	US-201615266752-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Mar 13, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

First claim

What is claimed is:

1. An integrated circuit (“IC”) package substrate, comprising a bottom surface comprising an array of contacts, the array of contacts comprising a plurality of data I/O contacts, wherein:
a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first portion of the bottom surface;
a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second portion of the bottom surface; and
the first portion and the second portion are reflectively symmetrical about a central axis.

2. The IC package substrate of claim 1 , the array of contacts further comprising a plurality of ground (“GND”) contacts, wherein at least one GND contact of the plurality of GND contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.

3. The IC package substrate of claim 1 , the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts, wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.

4. The IC package substrate of claim 1 , wherein the first subset of the plurality of data I/O contacts comprises a first communications channel, and the second subset of the plurality of data I/O contacts comprises a second communications channel.

5. The IC package of claim 4 , the array of contacts further comprising a plurality of chip enable (“CE”) contacts, wherein a first subset of the plurality of CE contacts are reflectively symmetrical with a second subset of the plurality of CE contacts about the axis of symmetry.

6. The IC package of claim 5 , wherein the first subset of the CE contacts enables a first set of memory dies to at least one of send and receive signals via the first communications channel, and wherein the second subset of the CE contacts enables a second set of memory dies to at least one of send and receive signals via the second communications channel.

7. The IC package of claim 1 , the array of contacts further comprising a plurality of supply voltage (“Vcc”) and GND contacts arranged in parallel axes at edges of the array of contacts, wherein the first and second C-shaped layouts are centered between the parallel axes.

8. An integrated circuit (“IC”) package substrate, comprising a bottom surface comprising an array of contacts, the array of contacts comprising a plurality of data I/O contacts, wherein:
a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first side of the bottom surface;
a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second side of the bottom surface; and
the first side and the second side are reflectively symmetrical about a central axis, wherein
the array of contacts further comprising a plurality of ground (“GND”) contacts, wherein only two GND contacts of the plurality of GND contacts are surrounded by the data I/O contacts of the first and second subsets of the plurality of data I/O contacts.

9. The IC package substrate of claim 8 , the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts, wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.

10. The IC package substrate of claim 8 , wherein the first subset of the plurality of data I/O contacts comprises a first communications channel, and the second subset of the plurality of data I/O contacts comprises a second communications channel.

11. The IC package substrate of claim 8 , the array of contacts further comprising a plurality of write enable (“WE”) contacts arranged in two parallel diagonal axes between the first and second C-shaped layouts.

12. The IC package substrate of claim 8 , wherein a first subset of the WE contacts is arranged in a first of the two parallel diagonal axes adjacent to the first C-shaped layout, and wherein a second subset of the WE contacts is arranged in a second of the two parallel diagonal axes adjacent to the second C-shaped layout.

13. The IC package substrate of claim 12 , wherein the first subset of the WE contacts maps onto corresponding WE contacts of the second subset of the plurality of WE contacts upon 180° rotation about the point of symmetry located on the central axis.

14. A semiconductor package comprising:
an integrated circuit (“IC”) package substrate comprising a plurality of conductive contacts formed on a bottom surface of the IC package substrate, wherein the plurality of conductive contacts further comprise a plurality of data I/O contacts and a plurality of ground (“GND”) contacts,
wherein only two GND contacts of the plurality of GND contacts are surrounded by the data I/O contacts associated with respective ones of first and second C-shaped layout of subsets of the plurality conductive contacts.

15. The semiconductor package of claim 14 , wherein a first one of the only two GND contacts is associated with first C-shaped layout, and wherein a second one of the only two GND contacts is associated with the second C-shaped layout.

16. The semiconductor package of claim 14 , wherein:
the first C-shaped layout, corresponding to a first communications channel, is arranged on a first side of the bottom surface of the IC package substrate; and
the second C-shaped layout, corresponding to a second communications channel, is arranged on a second side of the bottom surface of the IC package substrate.

17. The semiconductor package of claim 14 , wherein the IC package substrate comprises one of a land grid array (“LGA”), ball grid array (“BGA”), and a pin grid array (“PGA”).

Assignees

• Apple Inc

Inventors

• Fai Anthony
• Boyle Evan R
• Yang Zhiping
• Wu Zhonghua

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W42/271

  the arrangements being between stacked chips · CPC title