Semiconductor device

Patent metadata

Field	Value
Publication number	US-9583441-B2
Application number	US-201514809070-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Aug 7, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiO (1-x) N x (where x>0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an interlayer insulator film provided over the substrate,
an insulator film provided over the interlayer insulator film, thinner than the interlayer insulator film, and comprised of SiO (1-x) N x (where x>0.1); and
an interconnection provided over the insulator film,
wherein the interconnection includes a first layer on the insulator film and a second layer provided over the first layer,
wherein the first layer includes at least one of TiN, TaN, WN, and RuN, and
wherein the second layer is a W layer.

2. The semiconductor device according to claim 1 , wherein the insulator film has a thickness of 10 to 100 nm.

3. The semiconductor device according to claim 1 , wherein the first layer has an oxygen concentration of 2 at % or less.

4. A semiconductor device, comprising:
a substrate;
a multilayer interconnection layer provided over the substrate;
a bit line provided over a first insulator layer of the multilayer interconnection layer;
a capacitive element provided in a layer above the first insulator layer of the multilayer interconnection layer; and
a transistor provided in/on the substrate, and coupling the bit line to the capacitive element,
wherein the first insulator layer is comprised of SiO (1-x) N x (where x>0.1), and
wherein the bit line includes a first layer and a second layer provided over the first layer,
wherein the first layer includes at least one of TiN, TaN, WN, and RuN, and
wherein the second layer is formed of a material having a resistance lower than the first layer.

5. A semiconductor device, comprising:
a substrate;
an insulator layer provided over the substrate, and having a trench; and
a conductive layer filling the trench,
wherein the insulator layer includes a first insulator film having the trench, and a second insulator film provided on the side face of the trench,
wherein the second insulator film is a SiO (1-x) N x film,
wherein at least a side face of the trench is comprised of a SiO (1-x) N x (where x>0.1) film,
wherein the conductive layer includes a first layer provided over the side face and a bottom of the trench, and
wherein the first layer includes at least one of TiN, TaN, WN, and RuN.

6. The semiconductor device according to claim 5 , wherein the insulator layer is a SiO (1-x) N x film.

7. The semiconductor device according to claim 5 , wherein the conductive layer acts as an interconnection, and includes a W layer provided over the first layer.

8. The semiconductor device according to claim 6 , further comprising a capacitive element filling the trench,
wherein the conductive layer acts as a lower electrode of the capacitive element.

9. A semiconductor device, comprising:
an insulator film;
an interconnection provided over the insulator film; and
a barrier metal film located between the interconnection and the insulator film,
wherein the insulator film is formed of a material that releases oxygen more poorly than SiO 2 , and
wherein a profile of oxygen concentration in SIMS analysis in a thickness direction of the barrier metal film is not asymmetric with reference to the thickness center of the barrier metal.

Assignees

• Renesas Electronics Corp

Inventors

• Ogura Takashi
• Usami Tatsuya
• Kodama Satoshi
• Ueno Shuuichirou
• Itou Satoshi
• Itou Takamasa

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/033

  in openings in dielectrics · CPC title