Embedding thin chips in polymer

Patent metadata

Field	Value
Publication number	US-9583428-B2
Application number	US-201514859112-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Oct 9, 2012
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.

First claim

What is claimed:

1. An apparatus comprising:
A) a substrate comprising a standoff well region, wherein:
the substrate comprises a layer of a first conductive material disposed on a layer of a flexible polymer that is further stretchable; and
a patterned portion of the first conductive material comprises a standoff bordering a portion of exposed flexible polymer, thereby forming the standoff well region; and

B) a thin chip disposed within the standoff well region on a portion of the exposed flexible polymer proximate to the standoff,
wherein a height of the standoff is comparable to a height of the thin chip.

2. The apparatus of claim 1 , wherein the thin chip is a thinned chip.

3. The apparatus of claim 1 , wherein the thin chip is disposed within the standoff well region such that the height of the standoff is greater than or about equal to the height of the thin chip.

4. The apparatus of claim 1 , further comprising:
a polymer sheet disposed over the substrate;
at least one via formed through the polymer sheet; and
a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

5. The apparatus of claim 1 , wherein the standoff completely surrounds the thin chip.

6. The apparatus of claim 1 , wherein a dielectric material is disposed between the standoff and a portion of the thin chip.

7. The apparatus of claim 1 , further comprising at least one additional layer disposed on the first conductive material or on the flexible polymer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.

8. The apparatus of claim 1 , wherein the standoff includes a plurality of standoffs that define the standoff well region, the standoff configured to border at least three sides of the thin chip.

9. The apparatus of claim 1 , wherein the standoff includes at least one gap between the plurality of standoffs that define the standoff well region.

10. The apparatus of claim 1 , wherein the standoff includes a plurality of standoffs that define the standoff well region, the standoff being configured to border all sides of the thin chip, the standoff further including at least one gap between the plurality of standoffs that define the standoff well region.

11. A method for embedding thin chips, the method comprising:
A) providing a substrate comprising a standoff well region, wherein:
the substrate comprises a first conductive material layer disposed on a flexible polymer layer, wherein the flexible polymer layer is further stretchable; and
at least a portion of the first conductive material layer is patterned to form a standoff bordering a portion of exposed flexible polymer, thereby forming the standoff well region; and

B) disposing a thin chip on a portion of the exposed flexible polymer proximate to the standoff such that a height of the standoff is comparable to a height of the thin chip.

12. The method of claim 11 , wherein the height of the standoff is greater than or about equal to a height of a thin chip.

13. The method of claim 11 , further comprising:
disposing a polymer sheet over the substrate;
forming at least one via through the polymer sheet; and
disposing a conductive material on a portion of the second polymer sheet proximate to the at least one via, such that the conductive material forms an electrical communication with an electrical contact of the thin chip.

14. The method of claim 11 , further comprising disposing at least one additional layer on the first conductive material layer or on the flexible polymer layer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of an apparatus including the embedded thin chips.

15. An apparatus comprising:
A) a substrate comprising a polymer well region, wherein:
the substrate comprises a flexible polymer layer disposed on a first conductive material layer, wherein the flexible polymer is further stretchable;
a cavity is formed in at least a portion of the flexible polymer layer to form at least one polymer wall bordering a portion of exposed first conductive material layer, thereby forming the polymer well region; and

B) a thin chip disposed within the polymer well region on at least a portion of the exposed first conductive material layer proximate to the at least one polymer wall.

16. The apparatus of claim 15 , wherein the thin chip is a thinned chip.

17. The apparatus of claim 15 , wherein the thin chip is disposed within the polymer well region such that the height of the at least one polymer wall is less than the height of the thin chip.

18. The apparatus of claim 15 , further comprising:
a polymer sheet disposed over the substrate;
at least one via formed through the polymer sheet; and
a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

19. The apparatus of claim 15 , wherein the at least one polymer wall completely surrounds the thin chip.

20. The apparatus of claim 15 , wherein a dielectric material is disposed between the at least one polymer wall and a portion of the thin chip.

21. The apparatus of claim 15 , further comprising at least one additional layer disposed on the first conductive material layer or on the flexible polymer layer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of the apparatus.

22. A method for embedding thin chips, the method comprising:
A) providing a substrate comprising a polymer well region, the substrate comprising a first conductive material layer and a flexible polymer layer that is further stretchable, the polymer well region comprising at least one polymer wall formed from a portion of the flexible polymer layer and a base region formed from at least a portion of the first conductive material layer; and
B) disposing a thin chip within the polymer well region on a portion of the first conductive material layer proximate to the at least one polymer wall.

23. The method of claim 22 , wherein the thin chip is disposed within the polymer well region such that the first conductive material layer is in physical and electrical communication with the thin chip.

24. The method of claim 22 , further comprising:
a polymer sheet disposed over the substrate;
at least one via formed through the polymer sheet; and
a second conductive material disposed on a portion of the polymer sheet proximate to the at least one via, such that the second conductive material forms an electrical communication with an electrical contact of the thin chip.

25. The method of claim 22 , further comprising disposing at least one additional layer on the first conductive material layer or on the flexible polymer layer, wherein the at least one additional layer positions the thin chip at a neutral mechanical plane of an apparatus that include the embedded thin chips.

Assignees

• Mc10 Inc

Inventors

• Rafferty Conor
• Dalal Mitul

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title