Inverted trapezoidal recess for epitaxial growth

Patent metadata

Field	Value
Publication number	US-9583379-B2
Application number	US-201514936372-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Jul 30, 2010
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
isolation trenches extending into the semiconductor substrate, wherein a recess in the semiconductor substrate extends between the isolation trenches, the recess having a bottom surface and sidewalls, the recess having sidewalls extending at an obtuse angle relative to the bottom surface of the recess, surfaces of the sidewalls having a (111) crystal orientation; and
a compound semiconductor layer in the recess, the compound semiconductor layer extending continuously between the isolation trenches and contacting each of the isolation trenches.

2. The semiconductor device of claim 1 , wherein the semiconductor substrate has a (001) crystal orientation.

3. The semiconductor device of claim 1 , wherein the compound semiconductor layer is a group III-V semiconductor layer.

4. The semiconductor device of claim 3 , wherein the group III-V semiconductor layer comprises GaN.

5. The semiconductor device of claim 1 , wherein the compound semiconductor layer comprises threading dislocations that extend from the sidewalls of the recess.

6. The semiconductor device of claim 5 , wherein the threading dislocations terminate at sidewalls of the isolation trenches.

7. The semiconductor device of claim 1 , wherein the sidewalls of the recess extend to a bottom of the isolation trenches.

8. A method of forming a semiconductor device, the method comprising:
forming trenches in a substrate;
filling the trenches with a dielectric material;
performing one or more etch processes to form an inverted trapezoidal recess in the substrate between the trenches, the inverted trapezoidal recess having a bottom surface and sidewalls extending from the bottom surface to the dielectric material, the sidewalls of the inverted trapezoidal recess having (111) facet planes of the substrate, an angle between the bottom surface and the sidewalls being an obtuse angle; and
epitaxially growing a compound semiconductor material in the inverted trapezoidal recess, the compound semiconductor material extending continuously and contacting the dielectric material in each of the trenches.

9. The method of claim 8 , wherein the substrate comprises silicon.

10. The method of claim 8 , wherein the substrate comprises a semiconductor-on-insulator.

11. The method of claim 8 , wherein an upper surface of the substrate has a (001) crystal orientation.

12. The method of claim 8 , wherein the compound semiconductor material is a III-V semiconductor.

13. The method of claim 12 , wherein the III-V semiconductor comprises GaN.

14. The method of claim 8 , wherein the one or more etch processes is performed at least in part by etching using a solution of ammonium hydroxide (NH3OH) or tetra-methyl ammonium hydroxide (TMAH).

15. A method of forming a semiconductor device, the method comprising:
performing a first etch process to form a first recess in a substrate, the first recess having first sidewalls;
performing a second etch process to extend the first recess into the substrate to form a second recess, the second recess having a bottom surface and second sidewalls extending from the bottom surface to the first sidewalls, the second sidewalls of the second recess having a (111) crystal orientation, the first etch process being a different etch process from the second etch process; and
epitaxially growing a compound semiconductor material on the substrate in the second recess, the compound semiconductor material having dislocations extending from the second sidewalls of the second recess and terminating along the first sidewalls.

16. The method of claim 15 , wherein the first etch process comprises an isotropic etch process.

17. The method of claim 16 , wherein the second etch process comprises using a solution of ammonium hydroxide (NH3OH) or tetra-methyl ammonium hydroxide (TMAH).

18. The method of claim 15 , wherein the first etch process and the second etch process is performed between dielectric features.

19. The method of claim 18 , wherein the second etch process extends the second recess under the dielectric features.

20. The method of claim 18 , wherein the dislocations terminate at the dielectric features.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ko Chih-Hsin
• Wu Cheng-Hsien
• Wann Clement Hsingjen

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title